SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation

Macromodeling-Simulation process for signal integrity verifications has become necessary for the high speed circuit system design. This paper aims to introduce a “VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques” framework (known as SIM-DSP framework), which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase. Core identification modules and peripheral (pre-/post-)processing modules have been developed and assembled to form a verification flow. In particular, a single-step discrete cosine transform truncation (DCTT) module has been developed for modeling-simulation process. In DCTT, the response modeling problem is classified as a signal compression problem, wherein the system response can be represented by a truncated set of non-pole based DCT bases, and error can be analyzed through Parseval’s theorem. Practical examples are given to show the applicability of our proposed framework

Thermal Noise Compliant Synthesis of Linear Lumped Macromodels

This paper addresses the synthesis of equivalent circuits from black box state-space macromodels, as produced by model order reduction or rational curve fitting schemes. The emphasis is here on thermal noise compliance, intended as the guarantee that the produced netlists can be safely used in standard circuit solvers to perform thermal noise analysis, in addition to usual DC, AC, and transient simulations. Due to the fact that SNR is a key figure of merit in nearly all signal processing analog circuits, noise analysis is mandatory in design and verification of most analog and RF/millimeter-wave electronic applications. However, common macromodel synthesis approaches rely on components that do not (and cannot) have an associated thermal noise model, such as controlled sources or negative circuit elements. Therefore, macromodel-based noise analyses are generally not possible with currently available approaches. We propose a circuit realization derived from the classical resistance extraction synthesis, with suitable modifications for enhancing macromodel sparsity and efficiency. The resulting equivalent netlist, which is compatible with any standard circuit solver, is shown to produce exact noise characteristics, even if its elements are derived through a mathematical procedure, totally unrelated to the actual topology of the physical system under modeling. The procedure is validated by several examples

Design tools for rapid multidomain prototyping of power electronic systems

The need for multidisciplinary virtual prototyping in power electronics has been well established however design tools capable of facilitating a rapid, iterative virtual design process do not exist. A key challenge in developing such tools is identifying and developing modelling techniques which can account for 3D, geometrical design choices without unduly affecting simulation speed. This challenge has been addressed in this work using model order reduction techniques and a prototype power electronic design tool incorporating these techniques is presented. A relevant electro-thermal power module design example is then used to demonstrate the performance of the software and model order reduction techniques. Five design iterations can be evaluated, using 3D inductive and thermal models, under typical operating and startup conditions on a desktop PC in less than 15 minutes. The results are validated experimentally for both thermal and electrical domains

The Partial Elements Equivalent Circuit Method: The State Of The Art

This year marks about half a century since the birth of the technique known as the partial element equivalent circuit modeling approach. This method was initially conceived to model the behavior of interconnect-type problems for computer-integrated circuits. An important industrial requirement was the computation of general inductances in integrated circuits and packages. Since then, the advances in methods and applications made it suitable for modeling a large class of electromagnetic problems, especially in the electromagnetic compatibility (EMC)/signal and power integrity (SI/PI) areas. The purpose of this article is to present an overview of all aspects of the method, from its beginning to the present day, with special attention to the developments that have made it suitable for EMC/SI/PI problems

Physical parameter-aware Networks-on-Chip design

PhD ThesisNetworks-on-Chip (NoCs) have been proposed as a scalable, reliable and power-efficient communication fabric for chip multiprocessors (CMPs) and multiprocessor systems-on-chip (MPSoCs). NoCs determine both the performance and the reliability of such systems, with a significant power demand that is expected to increase due to developments in both technology and architecture. In terms of architecture, an important trend in many-core systems architecture is to increase the number of cores on a chip while reducing their individual complexity. This trend increases communication power relative to computation power. Moreover, technology-wise, power-hungry wires are dominating logic as power consumers as technology scales down. For these reasons, the design of future very large scale integration (VLSI) systems is moving from being computation-centric to communication-centric. On the other hand, chip’s physical parameters integrity, especially power and thermal integrity, is crucial for reliable VLSI systems. However, guaranteeing this integrity is becoming increasingly difficult with the higher scale of integration due to increased power density and operating frequencies that result in continuously increasing temperature and voltage drops in the chip. This is a challenge that may prevent further shrinking of devices. Thus, tackling the challenge of power and thermal integrity of future many-core systems at only one level of abstraction, the chip and package design for example, is no longer sufficient to ensure the integrity of physical parameters. New designtime and run-time strategies may need to work together at different levels of abstraction, such as package, application, network, to provide the required physical parameter integrity for these large systems. This necessitates strategies that work at the level of the on-chip network with its rising power budget. This thesis proposes models, techniques and architectures to improve power and thermal integrity of Network-on-Chip (NoC)-based many-core systems. The thesis is composed of two major parts: i) minimization and modelling of power supply variations to improve power integrity; and ii) dynamic thermal adaptation to improve thermal integrity. This thesis makes four major contributions. The first is a computational model of on-chip power supply variations in NoCs. The proposed model embeds a power delivery model, an NoC activity simulator and a power model. The model is verified with SPICE simulation and employed to analyse power supply variations in synthetic and real NoC workloads. Novel observations regarding power supply noise correlation with different traffic patterns and routing algorithms are found. The second is a new application mapping strategy aiming vii to minimize power supply noise in NoCs. This is achieved by defining a new metric, switching activity density, and employing a force-based objective function that results in minimizing switching density. Significant reductions in power supply noise (PSN) are achieved with a low energy penalty. This reduction in PSN also results in a better link timing accuracy. The third contribution is a new dynamic thermal-adaptive routing strategy to effectively diffuse heat from the NoC-based threedimensional (3D) CMPs, using a dynamic programming (DP)-based distributed control architecture. Moreover, a new approach for efficient extension of two-dimensional (2D) partially-adaptive routing algorithms to 3D is presented. This approach improves three-dimensional networkon- chip (3D NoC) routing adaptivity while ensuring deadlock-freeness. Finally, the proposed thermal-adaptive routing is implemented in field-programmable gate array (FPGA), and implementation challenges, for both thermal sensing and the dynamic control architecture are addressed. The proposed routing implementation is evaluated in terms of both functionality and performance. The methodologies and architectures proposed in this thesis open a new direction for improving the power and thermal integrity of future NoC-based 2D and 3D many-core architectures

Model reduction of parasitic coupling networks of mixed-signal VLSI circuits

Purpose: This paper aims to present a method for the efficient reduction of networks modelling parasitic couplings in very-large-scale integration (VLSI) circuits. Design/methodology/approach: The parasitic effects are modelled by large RLC networks and current sources for the digital switching currents. Based on the determined behaviour of the digital modules, an efficient description of these networks is proposed, which allows for a more efficient model reduction than standard methods. Findings: The proposed method enables a fast and efficient simulation of the parasitic effects. Additionally, an extension of the reduction method to elements, which incorporate some supply voltage dependence to model the internal currents more precisely than independent current sources is presented. Practical implications: The presented method can be applied to large electrical networks, used in the modelling of parasitic effects, for reducing their size. A reduced model is created which can be used in investigations with circuit simulators requiring a lowered computational effort. Originality/value: Contrary to existing methods, the presented method includes the knowledge of the behaviour of the sources in the model to enhance the model reduction process. © Emerald Group Publishing Limited 0332-1649

Fast methods for full-wave electromagnetic simulations of integrated circuit package modules

Fast methods for the electromagnetic simulation of integrated circuit (IC) package modules through model order reduction are demonstrated. The 3D integration of multiple functional IC chip/package modules on a single platform gives rise to geometrically complex structures with strong electromagnetic phenomena. This motivates our work on a fast full-wave solution for the analysis of such modules, thus contributing to the reduction in design cycle time without loss of accuracy. Traditionally, fast design approaches consider only approximate electromagnetic effects, giving rise to lumped-circuit models, and therefore may fail to accurately capture the signal integrity, power integrity, and electromagnetic interference effects. As part of this research, a second order frequency domain full-wave susceptance element equivalent circuit (SEEC) model will be extracted from a given structural layout. The model so obtained is suitably reduced using model order reduction techniques. As part of this effort, algorithms are developed to produce stable and passive reduced models of the original system, enabling fast frequency sweep analysis. Two distinct projection-based second order model reduction approaches will be considered: 1) matching moments, and 2) matching Laguerre coefficients, of the original system's transfer function. Further, the selection of multiple frequency shifts in these schemes to produce a globally representative model is also studied. Use of a second level preconditioned Krylov subspace process allows for a memory-efficient way to address large size problems.Ph.D.Committee Chair: Swaminathan Madhavan; Committee Member: Papapolymerou John; Committee Member: Chatterjee Abhijit; Committee Member: Peterson Andrew; Committee Member: Sitaraman Sures

Model Order Reduction

An increasing complexity of models used to predict real-world systems leads to the need for algorithms to replace complex models with far simpler ones, while preserving the accuracy of the predictions. This three-volume handbook covers methods as well as applications. This third volume focuses on applications in engineering, biomedical engineering, computational physics and computer science

SCEE 2008 book of abstracts : the 7th International Conference on Scientific Computing in Electrical Engineering (SCEE 2008), September 28 – October 3, 2008, Helsinki University of Technology, Espoo, Finland

This report contains abstracts of presentations given at the SCEE 2008 conference.reviewe