Magnetic racetrack memory: from physics to the cusp of applications within a decade

Racetrack memory (RTM) is a novel spintronic memory-storage technology that has the potential to overcome fundamental constraints of existing memory and storage devices. It is unique in that its core differentiating feature is the movement of data, which is composed of magnetic domain walls (DWs), by short current pulses. This enables more data to be stored per unit area compared to any other current technologies. On the one hand, RTM has the potential for mass data storage with unlimited endurance using considerably less energy than today's technologies. On the other hand, RTM promises an ultrafast nonvolatile memory competitive with static random access memory (SRAM) but with a much smaller footprint. During the last decade, the discovery of novel physical mechanisms to operate RTM has led to a major enhancement in the efficiency with which nanoscopic, chiral DWs can be manipulated. New materials and artificially atomically engineered thin-film structures have been found to increase the speed and lower the threshold current with which the data bits can be manipulated. With these recent developments, RTM has attracted the attention of the computer architecture community that has evaluated the use of RTM at various levels in the memory stack. Recent studies advocate RTM as a promising compromise between, on the one hand, power-hungry, volatile memories and, on the other hand, slow, nonvolatile storage. By optimizing the memory subsystem, significant performance improvements can be achieved, enabling a new era of cache, graphical processing units, and high capacity memory devices. In this article, we provide an overview of the major developments of RTM technology from both the physics and computer architecture perspectives over the past decade. We identify the remaining challenges and give an outlook on its future

Area-Efficient Spin-Orbit Torque Magnetic Random-Access Memory

Spin-orbit torque magnetic random-access memory (SOT-MRAM) has shown promising potential to realize reliable, high-speed and energy-efficient on-chip memory. However, conventional SOT-MRAM requires two access transistors per cell. This limits the use of conventional SOT-MRAM in high-density memories. Thus, various architectures in the literature have been proposed to improve the area efficiency of the SOT-MRAM. In this chapter, these proposals are divided into two categories: non-diode-based SOT-MRAM and diode-based SOT-MRAM cells. The non-diode-based proposals may result in a 1-bit effective area saving up to 50% compared to the conventional SOT-MRAM, whereas the diode-based designs may result in 1-bit effective area-saving of up to 75%. However, the area saving may be accompanied by higher energy and reliability issue penalties. Therefore, here, the various proposals in the literature are presented, highlighting the pros and cons of each design. Moreover, the technology requirements to realize these proposals are discussed. Finally, the various designs are evaluated from both cell and system level perspectives

Ultrafast and low-energy switching in voltage-controlled elliptical pMTJ

Switching magnetization in a perpendicular magnetic tunnel junction (pMTJ) via voltage controlled magnetic anisotropy (VCMA) has shown the potential to markedly reduce the switching energy. However, the requirement of an external magnetic field poses a critical bottleneck for its practical applications. In this work, we propose an elliptical-shaped pMTJ to eliminate the requirement of providing an external field by an additional circuit. We demonstrate that a 10 nm thick in-plane magnetized bias layer (BL) separated by a metallic spacer of 3 nm from the free layer (FL) can be engineered within the MTJ stack to provide the 50 mT bias magnetic field for switching. By conducting macrospin simulation, we find that a fast switching in 0.38 ns with energy consumption as low as 0.3 fJ at a voltage of 1.6 V can be achieved. Furthermore, we study the phase diagram of switching probability, showing that a pulse duration margin of 0.15 ns is obtained and a low-voltage operation (~ 1 V) is favored. Finally, the MTJ scalability is considered, and it is found that scaling-down may not be appealing in terms of both the energy consumption and the switching time for the precession based VCMA switching.Comment: There are 28 pages and 5 figure

Toward a Unified Performance and Power Consumption NAND Flash Memory Model of Embedded and Solid State Secondary Storage Systems

This paper presents a set of models dedicated to describe a flash storage subsystem structure, functions, performance and power consumption behaviors. These models cover a large range of today's NAND flash memory applications. They are designed to be implemented in simulation tools allowing to estimate and compare performance and power consumption of I/O requests on flash memory based storage systems. Such tools can also help in designing and validating new flash storage systems and management mechanisms. This work is integrated in a global project aiming to build a framework simulating complex flash storage hierarchies for performance and power consumption analysis. This tool will be highly configurable and modular with various levels of usage complexity according to the required aim: from a software user point of view for simulating storage systems, to a developer point of view for designing, testing and validating new flash storage management systems

Design and Robustness Analysis on Non-volatile Storage and Logic Circuit

By combining the flexibility of MOS logic and the non-volatility of spintronic devices, spin-MOS logic and storage circuitry offer a promising approach to implement highly integrated, power-efficient, and nonvolatile computing and storage systems. Besides the persistent errors due to process variations, however, the functional correctness of Spin-MOS circuitry suffers from additional non-persistent errors that are incurred by the randomness of spintronic device operations, i.e., thermal fluctuations. This work quantitatively investigates the impact of thermal fluctuations on the operations of two typical Spin-MOS circuitry: one transistor and one magnetic tunnel junction (1T1J) spin-transfer torque random access memory (STT-RAM) cell and a nonvolatile latch design. A new nonvolatile latch design is proposed based on magnetic tunneling junction (MTJ) devices. In the standby mode, the latched data can be retained in the MTJs without consuming any power. Two types of operation errors can occur, namely, persistent and non-persistent errors. These are quantitatively analyzed by including models for process variations and thermal fluctuations during the read and write operations. A mixture importance sampling methodology is applied to enable yield-driven design and extend its application beyond memories to peripheral circuits and logic blocks. Several possible design techniques to reduce thermal induced non-persistent error rate are also discussed

Synthesis and characterization of bulk and thin film antimony-selenium phase change alloys

Phase change alloys have recently gained increasing attention due to their application in developing phase change random memory (PRAM) devices, as Flash memory based devices are rapidly approaching their technological limitations. The most dominant features of PRAM devices are its non-volatile nature, compatible with present day IC\u27s manufacturing process, high density, fast operation, low power consumption etc; Devices built on binary alloys such as Antimony - Selenium (SbSe) exhibit certain superior properties such as fast operation, reduced power consumption, economical etc. compared to that of ternary alloy (GST). In order to understand this behavior in detail, bulk SbxSe 100-x (40 ≤ x ≤ 70) alloys are synthesized and deposited as thin films on silicon (100) plane substrate. Series of experiments such as X-ray diffraction analysis (XRD), Energy dispersive X-ray diffraction (EDAX), Spectroscopic Ellipsometer, Hall test experiments are carried out to characterize both the bulk and thin films. EDAX experiments show the deviation between bulk and thin films compositions is less than 10%. Diffraction patterns of bulk exhibit orthorhombic structure, i.e., Sb2Se3 type where as thin films demonstrate amorphous behavior. Impact of annealing on thin films is studied by heating the films to 170°C under argon (Ar) ambience. Post annealing results of Sb40Se60 thin films show the crystal structure is orthorhombic and crystallization temperature (Tc) increases with increase in Sb content of the compound. Ellipsometry and Hall measurements of annealed films exhibit high refractive index (n), low extinction coefficient (k) and high carrier concentration with associated low carrier mobility. Further the conductivity of annealed Sb40Se60 thin films switches from p to n type