4,787 research outputs found
The Rolf of Test Chips in Coordinating Logic and Circuit Design and Layout Aids for VLSI
This paper emphasizes the need for multipurpose test chips and comprehensive procedures for use in supplying accurate input data to both logic and circuit simulators and chip layout aids. It is shown that the location of test structures within test chips is critical in obtaining representative data, because geometrical distortions introduced during the photomasking process can lead to
significant intrachip parameter variations. In order to transfer test chip designs quickly, accurately, and economically, a commonly accepted portable chip layout notation and commonly accepted parametric tester language are needed. In order to measure test chips more accurately and more rapidly, parametric testers with improved architecture need to be developed in conjunction with
innovative test structures with on-chip signal conditioning
Product assurance technology for custom LSI/VLSI electronics
The technology for obtaining custom integrated circuits from CMOS-bulk silicon foundries using a universal set of layout rules is presented. The technical efforts were guided by the requirement to develop a 3 micron CMOS test chip for the Combined Release and Radiation Effects Satellite (CRRES). This chip contains both analog and digital circuits. The development employed all the elements required to obtain custom circuits from silicon foundries, including circuit design, foundry interfacing, circuit test, and circuit qualification
Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector
The concept of capacitive coupling between sensors and readout chips is under
study for the vertex detector at the proposed high-energy CLIC electron
positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an
active High-Voltage CMOS sensor, designed to be capacitively coupled to the
CLICpix2 readout chip. The chip is implemented in a commercial nm HV-CMOS
process and contains a matrix of square pixels with m
pitch. First prototypes have been produced with a standard resistivity of
cm for the substrate and tested in standalone mode. The
results show a rise time of ns, charge gain of mV/ke and
e RMS noise for a power consumption of W/pixel. The
main design aspects, as well as standalone measurement results, are presented.Comment: 13 pages, 13 figures, 2 tables. Work carried out in the framework of
the CLICdp collaboratio
SIRENA: A CAD environment for behavioural modelling and simulation of VLSI cellular neural network chips
This paper presents SIRENA, a CAD environment for the simulation and modelling of mixed-signal VLSI parallel processing chips based on cellular neural networks. SIRENA includes capabilities for: (a) the description of nominal and non-ideal operation of CNN analogue circuitry at the behavioural level; (b) performing realistic simulations of the transient evolution of physical CNNs including deviations due to second-order effects of the hardware; and, (c) evaluating sensitivity figures, and realize noise and Monte Carlo simulations in the time domain. These capabilities portray SIRENA as better suited for CNN chip development than algorithmic simulation packages (such as OpenSimulator, Sesame) or conventional neural networks simulators (RCS, GENESIS, SFINX), which are not oriented to the evaluation of hardware non-idealities. As compared to conventional electrical simulators (such as HSPICE or ELDO-FAS), SIRENA provides easier modelling of the hardware parasitics, a significant reduction in computation time, and similar accuracy levels. Consequently, iteration during the design procedure becomes possible, supporting decision making regarding design strategies and dimensioning. SIRENA has been developed using object-oriented programming techniques in C, and currently runs under the UNIX operating system and X-Windows framework. It employs a dedicated high-level hardware description language: DECEL, fitted to the description of non-idealities arising in CNN hardware. This language has been developed aiming generality, in the sense of making no restrictions on the network models that can be implemented. SIRENA is highly modular and composed of independent tools. This simplifies future expansions and improvements.Comisión Interministerial de Ciencia y Tecnología TIC96-1392-C02-0
Mixed-signal CNN array chips for image processing
Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, the design of general purpose, programmable CNN chips with dimensions required for practical applications raises many challenging problems to analog designers. This is basically due to the fact that large silicon area means large development cost, large spatial deviations of design parameters and low production yield. CNN designers must face different issues to keep reasonable enough accuracy level and production yield together with reasonably low development cost in their design of large CNN chips. This paper outlines some of these major issues and their solutions
A programmable microsystem using system-on-chip for real-time biotelemetry
A telemetry microsystem, including multiple sensors, integrated instrumentation and a wireless interface has been implemented. We have employed a methodology akin to that for System-on-Chip microelectronics to design an integrated circuit instrument containing several "intellectual property" blocks that will enable convenient reuse of modules in future projects. The present system was optimized for low-power and included mixed-signal sensor circuits, a programmable digital system, a feedback clock control loop and RF circuits integrated on a 5 mm × 5 mm silicon chip using a 0.6 μm, 3.3 V CMOS process. Undesirable signal coupling between circuit components has been investigated and current injection into sensitive instrumentation nodes was minimized by careful floor-planning. The chip, the sensors, a magnetic induction-based transmitter and two silver oxide cells were packaged into a 36 mm × 12 mm capsule format. A base station was built in order to retrieve the data from the microsystem in real-time. The base station was designed to be adaptive and timing tolerant since the microsystem design was simplified to reduce power consumption and size. The telemetry system was found to have a packet error rate of 10<sup>-</sup><sup>3</sup> using an asynchronous simplex link. Trials in animal carcasses were carried out to show that the transmitter was as effective as a conventional RF device whilst consuming less power
Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector
We have developed two radiation-hard ASICs for optical data transmission in
the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical
Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission
from the detector, and a Bi-Phase Mark decoder chip to recover the control data
and 40 MHz clock received optically by a PIN diode. We have successfully
implemented both ASICs in 0.25 um CMOS technology using enclosed layout
transistors and guard rings for increased radiation hardness. We present
results from prototype circuits and from irradiation studies with 24 GeV
protons up to 57 Mrad (1.9 x 10e15 p/cm2).Comment: 8th Tropical Seminar on Innovative Particle and Radiation Detectors,
Siena, Italy (2002
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