Switching Activity Minimization for XOR Gate Decomposition

In this paper we focus on reduction of switching activity in combinational logic circuits. We are analyzing energy consumption of multi-input XOR gate where changes of inputs occur principally at different times at logic level. We obtain upper and lower bounds for switching activity in various combinations with decomposition of muli-phase input gate. This work presents the algorithm of synthesis for multi-input XOR gate with minimum switching activity. The results presented in this paper are useful for power estimation and low power design. More than 10 to 70 % reduction of in switching activity has been observed using this method.Статья рассматривает вопросы минимизации переключательной активности комбинационных схем. Представлен анализ энергопотребления многовходовых элементов «Исключающее ИЛИ» для случая, когда сигналы на входах меняют свое состояние прин­ципиально в различные моменты времени. Получены формулы, определяющие верх­нюю и нижнюю границы переключательной активности для различных вариантов де­композиции многовходовых элементов. В работе представлен алгоритм синтеза многовходового элемента «Исключающее ИЛИ» с минимальной переключательной активностью. Полученные результаты могут быть использованы для оценки энергопотребления и проектирования с пониженным энергопотреблением. Показано, что применение предложенного подхода позволяет на 10–70 % снизить переключательную активность

Study of the Power Consumption of Pseudo Random Bit Generator Circuits Implemented on FPGA

Pseudo Random Bit and Number Generator (PRB/NG) circuits being very widely used for security, compressive sensing and diverse other applications in telecommunications are studies in different aspects in the laboratory of Computer-aided Design in Telecommunications in Technical University-Sofia. Some results of this study are published in [1] where tests for randomness from the National Institute of Standards and Technology (NIST) suit are applied on commonly used PRB/NGs. Other aspects of the PRB/NG circuits study is their power consumption in the aim of green communications as noticed in [2,3] and the concern about low power consuming devices for Internet of Things’ (IoT) applications. A recent research, described in [4] has confirmed the strong influence of VHDL codes of a circuit design from a given specification and it’s illustrated for a 4-bit comparator circuit. This paper considers power consumption estimation results for a set of PRB/NG circuits in the aim to add power consumption constraints at the design stage for such circuits and to help optimal design selection with minimal power consumption for a given application. The PRB/NG circuits are implemented on XILINX FPGA devices and they are simulated with the Power analyzer option of VIVADO tool and XPE. The approach proposed can be useful for other classes of communication circuits

АНАЛИЗ ЭНЕРГОПОТРЕБЛЕНИЯ МНОГОВХОДОВОГО СУММАТОРА ПО МОДУЛЮ ДВА

Проводится анализ энергопотребления многовходового сумматора по модулю два, выполненного на основе двухвходовых элементов «исключающее ИЛИ», для случая, когда изменения логических уровней на входах сумматора происходят принципиально в различные моменты времени. Получены верхняя и нижняя оценки переключательной активности для различных вариантов реализации многовходового сумматора. Рассматривается алгоритм синтеза многовходового сумматора с минимальной переключательной активностью

Power Modeling of Cmos Digital Circuits with a Piecewise Linear Model

This paper presents the average power modeling of CMOS digital circuits with a piecewise linear (PWL) model. The innovation of the piecewise linear model in the average power evaluation against previous power models is to include, for the first time, the effects of the first-order channel capacitive currents into a power calculation. Also, the model in the evaluation of the average power supply current predicts the currents contributed to the short-circuit power, dynamic power, and switching power of parasitic capacitances. A first-order channel storage charge model is derived to compute the power consumption caused by the nonlinear parasitic capacitances in a transistor channel. The PWL modeling of average power was validated by comparing SPICE average power simulation from the power supply current. The proposed model was validated with a submicron CMOS 0.5 um process and a deep submicron 0.18 um process to test its portability as a technology-independent model.School of Electrical & Computer Engineerin

Power Consumption in XOR-Based Circuits

The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using different delay models such as unit delay, fanout delay, and random delay in power estimation of XOR dominated logic. Due to different possible implementations of XOR gate, we model the XOR gate as a basic gate and a complex static CMOS gate, respectively. Power dissipation due to (charging and discharging) internal node capacitances is also considered. I. Introduction Due to the increasing use of portable systems, e.g., notebook computers, personal digital assistants, and cellular phones, power is rapidly becoming as important a parameter as area and speed in the design of such systems [1]. At the system level, increasing complexity and higher density on boards result in previously unseen ..