Voltage island-driven floorplanning.

Ma, Qiang.Thesis (M.Phil.)--Chinese University of Hong Kong, 2008.Includes bibliographical references (leaves 78-80).Abstracts in English and Chinese.Abstract --- p.iAcknowledgement --- p.ivChapter 1 --- Introduction --- p.1Chapter 1.1 --- Background --- p.1Chapter 1.2 --- Floorplanning --- p.2Chapter 1.3 --- Motivations --- p.4Chapter 1.4 --- Design Implementation of Voltage Islands --- p.5Chapter 1.5 --- Problem Formulation --- p.8Chapter 1.6 --- Progress on the Problem --- p.10Chapter 1.7 --- Contributions --- p.12Chapter 1.8 --- Thesis Organization --- p.14Chapter 2 --- Literature Review on MSV --- p.15Chapter 2.1 --- Introduction --- p.15Chapter 2.2 --- MSV at Post-floorplan/Post Placement Stage --- p.16Chapter 2.2.1 --- """Post-Placement Voltage Island Generation under Performance Requirement""" --- p.16Chapter 2.2.2 --- """Post-Placement Voltage Island Generation""" --- p.18Chapter 2.2.3 --- """Timing-Constrained and Voltage-Island-Aware Voltage Assignment""" --- p.19Chapter 2.2.4 --- """Voltage Island Generation under Performance Requirement for SoC Designs""" --- p.20Chapter 2.2.5 --- """An ILP Algorithm for Post-Floorplanning Voltage-Island Generation Considering Power-Network Planning""" --- p.21Chapter 2.3 --- MSV at Floorplan/Placement Stage --- p.22Chapter 2.3.1 --- """Architecting Voltage Islands in Core-based System-on-a- Chip Designs""" --- p.22Chapter 2.3.2 --- """Voltage Island Aware Floorplanning for Power and Timing Optimization""" --- p.23Chapter 2.4 --- Summary --- p.27Chapter 3 --- MSV Driven Floorplanning --- p.29Chapter 3.1 --- Introduction --- p.29Chapter 3.2 --- Problem Formulation --- p.32Chapter 3.3 --- Algorithm Overview --- p.33Chapter 3.4 --- Optimal Island Partitioning and Voltage Assignment --- p.33Chapter 3.4.1 --- Voltage Islands in Non-subtrees --- p.35Chapter 3.4.2 --- Proof of Optimality --- p.36Chapter 3.4.3 --- Handling Island with Power Down Mode --- p.37Chapter 3.4.4 --- Speedup in Implementation and Complexity --- p.38Chapter 3.4.5 --- Varying Background Chip-level Voltage --- p.39Chapter 3.5 --- Simulated Annealing --- p.39Chapter 3.5.1 --- Moves --- p.39Chapter 3.5.2 --- Cost Function --- p.40Chapter 3.6 --- Experimental Results --- p.40Chapter 3.6.1 --- Extension to Minimize Level Shifters --- p.45Chapter 3.6.2 --- Extension to Consider Power Network Routing --- p.46Chapter 3.7 --- Summary --- p.46Chapter 4 --- MSV Driven Floorplanning with Timing --- p.49Chapter 4.1 --- Introduction --- p.49Chapter 4.2 --- Problem Formulation --- p.52Chapter 4.3 --- Algorithm Overview --- p.56Chapter 4.4 --- Voltage Assignment Problem --- p.56Chapter 4.4.1 --- Lagrangian Relaxation --- p.58Chapter 4.4.2 --- Transformation into the Primal Minimum Cost Flow Problem --- p.60Chapter 4.4.3 --- Cost-Scaling Algorithm --- p.64Chapter 4.4.4 --- Solution Transformation --- p.66Chapter 4.5 --- Simulated Annealing --- p.69Chapter 4.5.1 --- Moves --- p.69Chapter 4.5.2 --- Speeding up heuristic --- p.69Chapter 4.5.3 --- Cost Function --- p.70Chapter 4.5.4 --- Annealing Schedule --- p.71Chapter 4.6 --- Experimental Results --- p.71Chapter 4.7 --- Summary --- p.72Chapter 5 --- Conclusion --- p.76Bibliography --- p.8

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