6 research outputs found
On Coding Efficiency for Flash Memories
Recently, flash memories have become a competitive solution for mass storage.
The flash memories have rather different properties compared with the rotary
hard drives. That is, the writing of flash memories is constrained, and flash
memories can endure only limited numbers of erases. Therefore, the design goals
for the flash memory systems are quite different from these for other memory
systems. In this paper, we consider the problem of coding efficiency. We define
the "coding-efficiency" as the amount of information that one flash memory cell
can be used to record per cost. Because each flash memory cell can endure a
roughly fixed number of erases, the cost of data recording can be well-defined.
We define "payload" as the amount of information that one flash memory cell can
represent at a particular moment. By using information-theoretic arguments, we
prove a coding theorem for achievable coding rates. We prove an upper and lower
bound for coding efficiency. We show in this paper that there exists a
fundamental trade-off between "payload" and "coding efficiency". The results in
this paper may provide useful insights on the design of future flash memory
systems.Comment: accepted for publication in the Proceeding of the 35th IEEE Sarnoff
Symposium, Newark, New Jersey, May 21-22, 201
Trajectory Codes for Flash Memory
Flash memory is well-known for its inherent asymmetry: the flash-cell charge
levels are easy to increase but are hard to decrease. In a general rewriting
model, the stored data changes its value with certain patterns. The patterns of
data updates are determined by the data structure and the application, and are
independent of the constraints imposed by the storage medium. Thus, an
appropriate coding scheme is needed so that the data changes can be updated and
stored efficiently under the storage-medium's constraints.
In this paper, we define the general rewriting problem using a graph model.
It extends many known rewriting models such as floating codes, WOM codes,
buffer codes, etc. We present a new rewriting scheme for flash memories, called
the trajectory code, for rewriting the stored data as many times as possible
without block erasures. We prove that the trajectory code is asymptotically
optimal in a wide range of scenarios.
We also present randomized rewriting codes optimized for expected performance
(given arbitrary rewriting sequences). Our rewriting codes are shown to be
asymptotically optimal.Comment: Submitted to IEEE Trans. on Inform. Theor
Implementing Write Compression in Flash Memory Using Zeckendorf Two-Round Rewriting Codes
Flash memory has become increasingly popular as the underlying storage technology for high-performance nonvolatile storage devices. However, while flash offers several benefits over alternative storage media, a number of limitations still exist within the current technology. One such limitation is that programming (altering a bit from its default value) and erasing (returning a bit to its default value) are asymmetric operations in flash memory devices: a flash memory can be programmed arbitrarily, but can only be erased in relatively large batches of storage bits called blocks, with block sizes ranging from 512K up to several megabytes. This creates a situation where relatively small write operations to the drive can potentially require reading out, erasing, and rewriting many times more data than the initial operation would normally require if that write would result in a bit erase operation. Prior work suggests that the performance impact of these costly block erase cycles can be mitigated by using a rewriting code, increasing the number of writes that can be performed on the same location in memory before an erase operation is required. This paper provides an implementation of this rewriting code, both as a software program written in C and as a SystemVerilog FPGA circuit specification, and discusses many of the additional design considerations that would be necessary to integrate such a rewriting code with current file storage techniques
Algorithms and Data Representations for Emerging Non-Volatile Memories
The evolution of data storage technologies has been extraordinary. Hard disk drives
that fit in current personal computers have the capacity that requires tons of transistors
to achieve in 1970s. Today, we are at the beginning of the era of non-volatile memory
(NVM). NVMs provide excellent performance such as random access, high I/O speed, low
power consumption, and so on. The storage density of NVMs keeps increasing following
Moore’s law. However, higher storage density also brings significant data reliability issues.
When chip geometries scale down, memory cells (e.g. transistors) are aligned much closer
to each other, and noise in the devices will become no longer negligible. Consequently,
data will be more prone to errors and devices will have much shorter longevity.
This dissertation focuses on mitigating the reliability and the endurance issues for two
major NVMs, namely, NAND flash memory and phase-change memory (PCM). Our main
research tools include a set of coding techniques for the communication channels implied
by flash memory and PCM. To approach the problems, at bit level we design error
correcting codes tailored for the asymmetric errors in flash and PCM, we propose joint
coding scheme for endurance and reliability, error scrubbing methods for controlling storage
channel quality, and study codes that are inherently resisting to typical errors in flash
and PCM; at higher levels, we are interested in analyzing the structures and the meanings
of the stored data, and propose methods that pass such metadata to help further improve
the coding performance at bit level. The highlights of this dissertation include the first
set of write-once memory code constructions which correct a significant number of errors,
a practical framework which corrects errors utilizing the redundancies in texts, the first
report of the performance of polar codes for flash memories, and the emulation of rank
modulation codes in NAND flash chips
Towards Endurable, Reliable and Secure Flash Memories-a Coding Theory Application
Storage systems are experiencing a historical paradigm shift from hard disk to nonvolatile memories due to its advantages such as higher density, smaller size and non-volatility. On the other hand, Solid Storage Disk (SSD) also poses critical challenges to application and system designers. The first challenge is called endurance. Endurance means flash memory can only experience a limited number of program/erase cycles, and after that the cell quality degradation can no longer be accommodated by the memory system fault tolerance capacity. The second challenge is called reliability, which means flash cells are sensitive to various noise and disturbs, i.e., data may change unintentionally after experiencing noise/disturbs. The third challenge is called security, which means it is impossible or costly to delete files from flash memory securely without leaking information to possible eavesdroppers.
In this dissertation, we first study noise modeling and capacity analysis for NAND flash memories (which is the most popular flash memory in market), which gains us some insight on how flash memories are working and their unique noise. Second, based on the characteristics of content-replication codewords in flash memories, we propose a joint decoder to enhance the flash memory reliability. Third, we explore data representation schemes in flash memories and optimal rewriting code constructions in order to solve the endurance problem. Fourth, in order to make our rewriting code more practical, we study noisy write-efficient memories and Write-Once Memory (WOM) codes against inter-cell interference in NAND memories. Finally, motivated by the secure deletion problem in flash memories, we study coding schemes to solve both the endurance and the security issues in flash memories. This work presents a series of information theory and coding theory research studies on the aforesaid three critical issues, and shows that how coding theory can be utilized to address these challenges