Surface Potential-Based Polycrystalline-Silicon Thin-Film Transistors Compact Model by Nonequilibrium Approach

We propose a surface potential-based polycrystalline silicon thin-film transistors (poly-Si TFTs) compact model considering a nonequilibrium state. A drain current model considers grain boundary (GB) trap-related physical phenomena: composite mobility of GB and intragrain, GB bias-induced mobility modulation, transient behavior because of carrier capture and emission at GBs, pinch off voltage lowering, and GB trap-assisted leakage current. Besides, photoinduced current behavior is also considered by introducing quasi-Fermi potential. A capacitance model is derived from physically partitioned terminal charges and coupled to the drain current. This compact model allows us to accurately simulate static characteristics of various types of poly-Si TFTs, including temperature and luminance dependence. Furthermore, it succeeded to simulate frequency dependence of circuit performance derived from the trap-related transient behavior, which was verified by evaluating delay time in a 21-stage inverter chain

A junctionless SONOS nonvolatile memory device constructed with in situ-doped polycrystalline silicon nanowires

In this paper, a silicon-oxide-nitride-silicon nonvolatile memory constructed on an n+-poly-Si nanowire [NW] structure featuring a junctionless [JL] configuration is presented. The JL structure is fulfilled by employing only one in situ heavily phosphorous-doped poly-Si layer to simultaneously serve as source/drain regions and NW channels, thus greatly simplifying the manufacturing process and alleviating the requirement of precise control of the doping profile. Owing to the higher carrier concentration in the channel, the developed JL NW device exhibits significantly enhanced programming speed and larger memory window than its counterpart with conventional undoped-NW-channel. Moreover, it also displays acceptable erase and data retention properties. Hence, the desirable memory characteristics along with the much simplified fabrication process make the JL NW memory structure a promising candidate for future system-on-panel and three-dimensional ultrahigh density memory applications

Thermal & electrical simulation for the development of solid-phase polycrystalline silicon TFTs

Solid phase crystallization (SPC) is a processing technique used for conversion of amorphous silicon (a-Si) to polycrystalline silicon (poly-Si). SPC can potentially be used as an alternative to excimer laser annealing to fabricate the semiconductor layer for thin-film transistors (TFTs) in active-matrix liquid crystal display (AMLCD). It is a technique suitable for large-area applications since it involves easily scalable thermal processes in the form of rapid thermal annealing (RTA) and furnace annealing (FA). The SPC parameter space involves the time and temperature of the FA, and the time, temperature, and number of pulses in the RTA process. In developing new process flows for thin-film transistors (TFTs) using SPC, thermal and electrical device simulation are invaluable tools. Comsol® was utilized to explore this SPC experimental parameter space, and provided important insight on temperature conditions not directly measureable on glass substrates (see Fig. 1). Silvaco\u27s Atlas® was utilized to evaluate the TFT response variables of sub-threshold slope (SS), threshold voltage (VT), and maximum current (Imax). Further, a procedure for fitting TFT device characteristics using Atlas was developed. From this simulation fit (see Fig. 2), theoretical trap state distributions for the semiconducting film can be extracted, as well as the trap state distributions at the oxide-semiconductor interfaces

Chromium Modified Crystallization of Silicon Thin Films Crystallized by Flash Lamp Annealing

Flash lamp annealing (FLA) is a method of quickly crystallizing large areas of amorphous silicon, which is a promising alternative to existing low-throughput laser annealing in the fabrication of low temperature polycrystalline silicon for thin film transistors in display applications [1]. However, FLA tends to promote dewet- ting of silicon and randomized void formation during melt-phase crystallization [2]. Chromium underlayers have been successfully used [3] to promote silicon adhesion in thicker films, but there are many potential interactions between Cr and Si, such as the formation of silicides and generation of electrical trap states, that may inhibit future transistor performance. The mechanism and effects of these interactions are not yet understood. This work investigates the efficacy of chromium adhesion layers in silicon crystallization by FLA. Various thicknesses and configurations of amorphous silicon, thin chromium, and silicon dioxide barriers were deposited on glass and subjected to FLA. The resulting material was analyzed with electron and atomic-probe microscopy and found to contain a unique repeated pattern of voids, trenches, and SEM-bright spots at the nanometer scale. Energy-dispersive X-ray spectroscopy confirmed the distribution of chromium in crystallized films to be discrete Cr-rich agglomerations 50-70 nm in diameter, with little metallic contamination outside of these isolated areas

Hot carrier induced leakage current instability in metal induced laterally crystallized n-type poly-silicon thin film transistors

Field enhanced leakage current characteristics of metal induced laterally crystallized polycrystalline silicon thin film transistors (poly-Si TFTs) under hot carrier (HC) stress are investigated, in both forward and reverse measurement mode, with varied stress gate/drain voltages and stress times. Degradation behaviors can be understood by the effect of HC stress on drain electrical field and on bulk poly-Si channel resistance. © 2006 IEEE

Effect of silicon thickness on the degradation mechanisms of sequential laterally solidified polycrystalline silicon TFTs during hot-carrier stress

We have investigated bias stress-induced aging effects in polycrystalline silicon thin-film transistors (poly-Si TFTs), as a function of the active layer thickness. Two aging mechanisms were identified: hot-carrier injection in the gate insulator and deep-state generation in the active "body." Hot-carrier injection was found dominant in devices having very thin (30 nm) or thick (100 nm) active layers. Deep-state generation dominated in devices having intermediate active layer thickness (50 nm). The fully depleted aspect of ultrathin active-layer devices, as well as their relative immunity to substantial degradation under bias stress, favor the implementation of thin active layer for the fabrication of high-performance and high-reliability poly-Si TFTs. © 2005 IEEE

Improvement of electrical characteristics for fluorine-ion-implanted poly-Si TFTs using ELC

[[abstract]]The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) is investigated in this letter. Experimental results have shown that fluorine ion implantation effectively minimized the trap state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, and high ON/OFF current ratio. Furthermore, the fluorine ions tended to segregate at the interface between the gate oxide and poly-Si layers during the excimer laser annealing, even without the extra deposition of pad oxide on the poly-Si film. The presence of fluorine obviously enhanced electrical reliability of poly-Si TFTs[[fileno]]2060116010008[[department]]工程與系統科學

Low frequency noise modeling of polycrystalline silicon thin-film transistors

A modified and improved low frequency model for polycrystalline silicon thin-film transistors (poly-Si TFTs) is developed in this paper. For small grain size poly-Si TFTs, based on carrier number fluctuations, an improvement of the standard low frequency noise model has been investigated to explain the noise characteristics of poly-Si TFTs. An exponential energy distribution for interface density of states is employed to model the interface trap capacitance. For large grain size devices, mobility fluctuations related to fluctuations of the grain boundary charges is used to describe the excess subthreshold noise. The anomalous noise increase behavior of poly-Si TFTs when operated in the kink regime is also studied and modeled. The proposed model and the experimental data agree well over a wide range of operation regimes

Study on Characteristics of Poly-Si TFTs With 3-D Finlike Channels Fabricated by Nanoimprint Technology

[[abstract]]This study addresses the characteristics of polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 3-D finlike channels fabricated using ultraviolet nanoimprint lithography. The poly-Si 3-D finlike channels with a line width/space ratio of about similar to 1:1 were fabricated and studied by scanning electron microscope and transmission electron microscopy. The poly-Si TFTs with 3-D finlike channels, fabricated using the nanoimprint technique, have superior performances in comparison to that with the single channel. Besides, the characteristics of poly-Si TFTs, such as the transfer characteristics, output drain current, transconductance, ON/OFF current ratio, subthreshold swing, and field-effective mobility, with respect to the width/space/height of 3-D finlike structures were also investigated. The proposed approach can be utilized to fabricated high-performance poly-Si TFTs or high-sensitivity biosensors at low cost.[[note]]SC