2,162 research outputs found

    SyRA: early system reliability analysis for cross-layer soft errors resilience in memory arrays of microprocessor systems

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    © 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Cross-layer reliability is becoming the preferred solution when reliability is a concern in the design of a microprocessor-based system. Nevertheless, deciding how to distribute the error management across the different layers of the system is a very complex task that requires the support of dedicated frameworks for cross-layer reliability analysis. This paper proposes SyRA, a system-level cross-layer early reliability analysis framework for radiation induced soft errors in memory arrays of microprocessor-based systems. The framework exploits a multi-level hybrid Bayesian model to describe the target system and takes advantage of Bayesian inference to estimate different reliability metrics. SyRA implements several mechanisms and features to deal with the complexity of realistic models and implements a complete tool-chain that scales efficiently with the complexity of the system. The simulation time is significantly lower than micro-architecture level or RTL fault-injection experiments with an accuracy high enough to take effective design decisions. To demonstrate the capability of SyRA, we analyzed the reliability of a set of microprocessor-based systems characterized by different microprocessor architectures (i.e., Intel x86, ARM Cortex-A15, ARM Cortex-A9) running both the Linux operating system or bare metal. Each system under analysis executes different software workloads both from benchmark suites and from real applications.Peer ReviewedPostprint (author's final draft

    Pre-Crash and In-Crash Car Occupant Safety Assessment

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    Tens of millions are annually injured in Road Traffic Accidents (RTAs) worldwide, while the estimated number of RTA fatalities amounted to 1.35 million in 2016. In Europe, car occupants hold the largest share (48%) of fatalities among all road users. The high fatality and injury numbers motivate the work of enhancing road traffic safety. A holistic safety assessment approach, considering both the pre- and the in-crash phase of a crash, has the potential to enhance real-world occupant protection evaluation, as well as facilitate the development of effective countermeasures. In standardized car occupant safety assessments, occupant surrogates of standardized anthropometries are employed in standardized postures, with the seat adjusted to a single predefined position. The vehicle is then subjected to predefined crash configurations with meticulously described impact points and angles. In contrast, real-world traffic crashes involve occupants of different shapes and sizes, who adjust the position of the seat and their posture on the seat differently, and the vehicles are subjected to diverse crash configurations (multiple impact locations, impact directions, and speed combinations). The overall aim of this thesis is to develop and apply methods, spanning from the pre-crash to the in-crash phase, capable of evaluating and enhancing the real-world occupant protection of future vehicles.The introduction of crash-avoidance systems has the potential to alter the crash configurations that future vehicles will be exposed to. A method for predicting crash configurations has been developed in this thesis and applied to highway driving, and urban intersection crashes. Performing counterfactual simulations of digitized real-world crashes, with and without the addition of a conceptual Automatic Emergency Braking system, provides a prediction of the remaining crashes. The use of a novel crash configuration definition, along with a purpose-designed clustering method, facilitates the reduction of the number of predicted crash configurations without sacrificing coverage of the diverse real-world situations. Three predicted crash configurations, representative of urban intersection crashes, were further analyzed during the in-crash phase. A Human Body Model was positioned in a wide range of occupant postures identified from the literature. The findings suggest that the lower extremity postures had the largest overall influence on the lower extremities, pelvis, and whole-body responses for all crash configurations. In the evaluated side-impacts, leaning the torso in the coronal plane affected the torso and head kinematics by changing the interaction with the vehicle’s interior. Additionally, in far-side impacts supporting the occupant’s arm on the center console resulted in increased torso excursions. Moreover, the upper extremity responses were consistently sensitive to posture variations of all body regions

    Layout regularity metric as a fast indicator of process variations

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    Integrated circuits design faces increasing challenge as we scale down due to the increase of the effect of sensitivity to process variations. Systematic variations induced by different steps in the lithography process affect both parametric and functional yields of the designs. These variations are known, themselves, to be affected by layout topologies. Design for Manufacturability (DFM) aims at defining techniques that mitigate variations and improve yield. Layout regularity is one of the trending techniques suggested by DFM to mitigate process variations effect. There are several solutions to create regular designs, like restricted design rules and regular fabrics. These regular solutions raised the need for a regularity metric. Metrics in literature are insufficient for different reasons; either because they are qualitative or computationally intensive. Furthermore, there is no study relating either lithography or electrical variations to layout regularity. In this work, layout regularity is studied in details and a new geometrical-based layout regularity metric is derived. This metric is verified against lithographic simulations and shows good correlation. Calculation of the metric takes only few minutes on 1mm x 1mm design, which is considered fast compared to the time taken by simulations. This makes it a good candidate for pre-processing the layout data and selecting certain areas of interest for lithographic simulations for faster throughput. The layout regularity metric is also compared against a model that measures electrical variations due to systematic lithographic variations. The validity of using the regularity metric to flag circuits that have high variability using the developed electrical variations model is shown. The regularity metric results compared to the electrical variability model results show matching percentage that can reach 80%, which means that this metric can be used as a fast indicator of designs more susceptible to lithography and hence electrical variations

    A fabrication guide for planar silicon quantum dot heterostructures

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    We describe important considerations to create top-down fabricated planar quantum dots in silicon, often not discussed in detail in literature. The subtle interplay between intrinsic material properties, interfaces and fabrication processes plays a crucial role in the formation of electrostatically defined quantum dots. Processes such as oxidation, physical vapor deposition and atomic-layer deposition must be tailored in order to prevent unwanted side effects such as defects, disorder and dewetting. In two directly related manuscripts written in parallel we use techniques described in this work to create depletion-mode quantum dots in intrinsic silicon, and low-disorder silicon quantum dots defined with palladium gates. While we discuss three different planar gate structures, the general principles also apply to 0D and 1D systems, such as self-assembled islands and nanowires.Comment: Accepted for publication in Nanotechnology. 31 pages, 12 figure

    Novel techniques for dopant profile monitoring

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    Investigation of hydraulic fracture complexity and the benefits of maximizing or minimizing complexity in unconventional resources

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    This dissertation discusses two separate, yet inter-related studies. The first study was an extension of historical work comparing transversely fractured versus longitudinally fractured horizontal wells in multiphase flow environment. The second study investigated hydraulic fracture complexities and the benefits of maximizing or minimizing complexities in unconventional resources and tight reservoirs. The main objective of this research was to investigate fracture complexity and its impact on well performance and economics. To achieve that objective, three different integrated completions and reservoir models were built. Two of the three models, a hybrid reservoir model and micro-seismic based SRV (stimulated reservoir volume) model, were built to capture presences of discrete fracture networks (DFN). The results of the DFN-based models were compared to an integrated planar fracture model, which had bi-wing fractures with limited or no fracture complexity. The second objective of this research was to determine reservoir permeability based cut-off criterion that can be used as guide when selecting whether to drill transversely fractured versus longitudinally fractured horizontal wells in multiphase flow environment. The reservoir models built for the multiphase flow would also investigate the effects of stress dependent permeability, adsorption gas and non-Darcy flow effect. The third objective of this research was to develop a calibrated hydraulic fracture and reservoir model for the Montney shale, particularly for the Upper Montney Formation. This model would help companies select best lateral placement options in the Upper Montney, stage perforation targets and model-based stage spacing --Abstract, page iii

    Control of Kaposi's Sarcoma-Associated Herpesvirus Reactivation Induced by Multiple Signals

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    The ability to control cellular functions can bring about many developments in basic biological research and its applications. The presence of multiple signals, internal as well as externally imposed, introduces several challenges for controlling cellular functions. Additionally the lack of clear understanding of the cellular signaling network limits our ability to infer the responses to a number of signals. This work investigates the control of Kaposi's sarcoma-associated herpesvirus reactivation upon treatment with a combination of multiple signals. We utilize mathematical model-based as well as experiment-based approaches to achieve the desired goals of maximizing virus reactivation. The results show that appropriately selected control signals can induce virus lytic gene expression about ten folds higher than a single drug; these results were validated by comparing the results of the two approaches, and experimentally using multiple assays. Additionally, we have quantitatively analyzed potential interactions between the used combinations of drugs. Some of these interactions were consistent with existing literature, and new interactions emerged and warrant further studies. The work presents a general method that can be used to quantitatively and systematically study multi-signal induced responses. It enables optimization of combinations to achieve desired responses. It also allows identifying critical nodes mediating the multi-signal induced responses. The concept and the approach used in this work will be directly applicable to other diseases such as AIDS and cancer

    Ultra-thin plasma nitrided oxide gate dielectrics for advanced MOS transistors

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    Ultra-thin plasma nitrided oxides have been optimized with the objective to decrease JG and maximize carrier mobility. It was found that while the base oxide cannot be aggressively scaled, plasma optimization yields better mobility thereby increase transistor performance. A summary of the EOT versus gate leakage current density of NMOS devices with plasma nitrided oxides is shown in Figure 5.19. EOT down to 1.2 nm has been achieved with a gate leakage current density of 40 A/cm2 at 1 V operating voltage
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