A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Progress on Carbon Nanotube BEOL Interconnects

This article is a review of the current progress and results obtained in the European H2020 CONNECT project. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, 2) modeling and simulation from atomistic to circuit-level bench-marking and performance prediction, and 3) characterization and electrical measurements. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a review and informative cornerstone on carbon nanotube interconnects

Atomistic to circuit-level modeling of doped SWCNT for on-chip interconnects

In this article, we present a hierarchical model for doped single-wall carbon nanotube (SWCNT) for on-chip interconnect application. We study the realistic CVD grown SWCNT with defects and contacts, which induce important resistance values and worsens SWCNT on-chip interconnect performance. We investigate the fundamental physical mechanism of doping in SWCNT with the purpose of improving its electrical conductivity as well as combining mitigating the effects of defects and large contact resistance. The atomistic model provides insights on statistical variations of the number of conducting channels of doped SWCNT and SWCNT resistance variation with a various number of vacancy defects configurations. Based on atomistic simulations, we develop circuit-level models to simulate SWCNT interconnects and understand the impact of doping, defects, and contacts. Simulation results show an 80% resistance reduction by doping. Additionally, we observe that doping can mitigate the effects of defects and limited impact on contact resistance

Variability study of MWCNT local interconnects considering defects and contact resistances - Part II: impact of charge transfer doping

In this paper, the impact of charge transfer doping on the variability of multiwalled carbon nanotube (MWCNT) local interconnects is studied by experiments and simulations. We calculate the number of conducting channels of both metallic and semiconducting carbon nanotubes as a function of Fermi level shift due to doping based on the calculation of transmission coefficients. By using the MWCNT compact model proposed in Part I of this paper, we study the charge transfer doping of MWCNTs employing Fermi level shift to reduce the performance variability due to changes in diameter, chirality, defects, and contact resistance. Simulation results show that charge transfer doping can significantly improve MWCNT interconnect performance and variability by increasing the number of conducting channels of shells and degenerating semiconducting shells to metallic shells. As a case study on an MWCNT of 11 nm outer diameter, when the Fermi level shifts to 0.1 eV, up to ~80% of performance and standard deviation improvements are observed. Furthermore, a good match between experimental data and simulation results is observed, demonstrating the effectiveness of doping, the validity of the MWCNT compact model and proposed simulation methodology

Electronic transport in metallic carbon nanotubes with mixed defects within the strong localization regime

We study the electron transport in metallic carbon nanotubes (CNTs) with realistic defects of different types. We focus on large CNTs with many defects in the mesoscopic range. In a recent paper we demonstrated that the electronic transport in those defective CNTs is in the regime of strong localization. We verify by quantum transport simulations that the localization length of CNTs with defects of mixed types can be related to the localization lengths of CNTs with identical defects by taking the weighted harmonic average. Secondly, we show how to use this result to estimate the conductance of arbitrary defective CNTs, avoiding time consuming transport calculations

Carbon Nanotube Interconnects for End-of-Roadmap Semiconductor Technology Nodes

Advances in semiconductor technology due to aggressive downward scaling of on-chip feature sizes have led to rapid rises in resistivity and current density of interconnect conductors. As a result, current interconnect materials, Cu and W, are subject to performance and reliability constraints approaching or exceeding their physical limits. Therefore, alternative materials such as nanocarbons, metal silicides, and Ag nanowires are actively considered as potential replacements to meet such constraints. Among nanocarbons, carbon nanotube (CNT) is among the leading replacement candidate for on-chip interconnect vias due to its high aspect-ratio nanostructure and superior currentcarrying capacity to those of Cu, W, and other potential candidates. However, contact resistance of CNT with metal is a major bottleneck in device functionalization. To meet the challenge posed by contact resistance, several techniques are designed and implemented. First, the via fabrication and CNT growth processes are developed to increase the CNT packing density inside via and to ensure no CNT growth on via sidewalls. CNT vias with cross-sections down to 40 nm 40 nm are fabricated, which have linewidths similar to those used for on-chip interconnects in current integrated circuit manufacturing technology nodes. Then the via top contact is metallized to increase the total CNT area interfacing with the contact metal and to improve the contact quality and reproducibility. Current-voltage characteristics of individual fabricated CNT vias are measured using a nanoprober and contact resistance is extracted with a first-reported contact resistance extraction scheme for 40 nm linewidth. Based on results for 40 nm and 60 nm top-contact metallized CNT vias, we demonstrate that not only are their current-carrying capacities two orders of magnitude higher than their Cu and W counterparts, they are enhanced by reduced via resistance due to contact engineering. While the current-carrying capacities well exceed those projected for end-of-roadmap technology nodes, the via resistances remain a challenge to replace Cu and W, though our results suggest that further innovations in contact engineering could begin to overcome such challenge

Monolithically Patterned Wide-Narrow-Wide All-Graphene Devices

We investigate theoretically the performance advantages of all-graphene nanoribbon field-effect transistors (GNRFETs) whose channel and source/drain (contact) regions are patterned monolithically from a two-dimensional single sheet of graphene. In our simulated devices, the source/drain and interconnect regions are composed of wide graphene nanoribbon (GNR) sections that are semimetallic, while the channel regions consist of narrow GNR sections that open semiconducting bandgaps. Our simulation employs a fully atomistic model of the device, contact and interfacial regions using tight-binding theory. The electronic structures are coupled with a self-consistent three-dimensional Poisson's equation to capture the nontrivial contact electrostatics, along with a quantum kinetic formulation of transport based on non-equilibrium Green's functions (NEGF). Although we only consider a specific device geometry, our results establish several general performance advantages of such monolithic devices (besides those related to fabrication and patterning), namely the improved electrostatics, suppressed short-channel effects, and Ohmic contacts at the narrow-to-wide interfaces.Comment: 9 pages, 11 figures, 2 table