3 research outputs found

    ์ฐจ๋Ÿ‰์šฉ CIS Interface ๋ฅผ ์œ„ํ•œ All-Digital Phase-Locked Loop ์˜ ์„ค๊ณ„ ๋ฐ ๋ถ„์„

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    ํ•™์œ„๋…ผ๋ฌธ (์„์‚ฌ) -- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2021. 2. ์ •๋•๊ท .This thesis presents design techniques for All-Digital Phase-Locked Loop (ADPLL) assisting the automotive CMOS image sensor (CIS) interface. To target Gear 3 of the automotive physical system, the proposed AD-PLL has a wide operation range, low RMS jitter, and high PVT tolerance characteristics. Detailed analysis of the loop dynamics and the noise analysis of AD-PLL are done by using Matlab and Verilog behavioral modeling simulation before an actual design. Based on that analysis, the optimal DLF gain configurations are yielded, and also, accurate output responses and performance are predictable. The design techniques to reduce the output RMS jitter are discussed thoroughly and utilized for actual implementation. The proposed AD-PLL is fabricated in the 40 nm CMOS process and occupies an effective area of 0.026 mm2. The PLL output clock pulses exhibit an RMS jitter of 827 fs at 2 GHz. The power dissipation is 5.8 mW at 2 GHz, where the overall supply voltage domain is 0.9 V excluding the buffer which is 1.1 V domain.๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” ์ž๋™์ฐจ CMOS ์ด๋ฏธ์ง€ ์„ผ์„œ (CIS) ์ธํ„ฐํŽ˜์ด์Šค๋ฅผ ์ง€์›ํ•˜ ๋Š” AD-PLL ์„ ์ œ์•ˆํ•œ๋‹ค. Automotive Physical ์‹œ์Šคํ…œ์˜ Gear 3 ๋ฅผ ์ง€์›ํ•˜๊ธฐ ์œ„ํ•ด ์ œ์•ˆ๋œ AD-PLL ์€ 1.5 GHz ์—์„œ 3 GHz ์˜ ๋™์ž‘ ์ฃผํŒŒ์ˆ˜๋ฅผ ๊ฐ€์ง€๋ฉฐ, ๋‚ฎ ์€ RMS Jitter ๋ฐ PVT ๋ณ€ํ™”์— ๋Œ€ํ•œ ๋†’์€ ๋‘”๊ฐ์„ฑ์„ ๊ฐ–๋Š”๋‹ค. ์„ค๊ณ„์— ์•ž์„œ์„œ Matlab ๋ฐ Verilog Behavioral Simulation ์„ ํ†ตํ•ด Loop system ์˜ ์—ญํ•™์— ๋Œ€ํ•œ ์ž์„ธํ•œ ๋ถ„์„ ๋ฐ AD-PLL ์˜ Noise ๋ถ„์„์„ ์ˆ˜ํ–‰ํ•˜์˜€๊ณ , ์ด ๋ถ„์„์„ ๊ธฐ๋ฐ˜์œผ๋กœ ์ตœ์ ์˜ DLF gain ๊ณผ ์ •ํ™•ํ•œ ์ถœ๋ ฅ ์‘๋‹ต ๋ฐ ์„ฑ๋Šฅ์„ ์˜ˆ์ธก ํ•  ์ˆ˜ ์žˆ์—ˆ๋‹ค. ๋˜ํ•œ, ์ถœ๋ ฅ์˜ Phase Noise ์™€ RMS Jitter ๋ฅผ ์ค„์ด๊ธฐ ์œ„ํ•œ ์„ค๊ณ„ ๊ธฐ๋ฒ•์„ ์ž์„ธํžˆ ๋‹ค๋ฃจ๊ณ  ์žˆ์œผ๋ฉฐ ์ด๋ฅผ ์‹ค์ œ ๊ตฌํ˜„์— ํ™œ์šฉํ–ˆ๋‹ค. ์ œ์•ˆ๋œ ํšŒ๋กœ๋Š” 40 nm CMOS ๊ณต์ •์œผ๋กœ ์ œ์ž‘๋˜์—ˆ์œผ๋ฉฐ Decoupling Cap ์„ ์ œ์™ธํ•˜๊ณ  0.026 mm2 ์˜ ์œ ํšจ ๋ฉด์ ์„ ์ฐจ์ง€ํ•œ๋‹ค. ์ธก์ •๋œ ์ถœ๋ ฅ Clock ์‹ ํ˜ธ์˜ RMS Jitter ๊ฐ’์€ 2 GHz ์—์„œ 827 fs ์ด๋ฉฐ, ์ด 5.8 mW์˜ Power ๋ฅผ ์†Œ๋น„ํ•œ๋‹ค. ์ด ๋•Œ, ์ „์ฒด์ ์ธ ๊ณต๊ธ‰ ์ „์••์€ 0.9 V ์ด๋ฉฐ, Buffer ์˜ Power ๋งŒ์ด 1.1 V ๋ฅผ ์‚ฌ์šฉํ•˜ ์˜€๋‹ค.ABSTRACT I CONTENTS II LIST OF FIGURES IV LIST OF TABLES VII CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 CHAPTER 2 BACKGROUND ON ALL-DIGITAL PLL 4 2.1 OVERVIEW 4 2.2 BUILDING BLOCKS OF AD-PLL 7 2.2.1 TIME-TO-DIGITAL CONVERTER 7 2.2.2 DIGITALLY-CONTROLLED OSCILLATOR 10 2.2.3 DIGITAL LOOP FILTER 13 2.2.4 DELTA-SIGMA MODULATOR 16 2.3 PHASE NOISE ANALYSIS OF AD-PLL 20 2.3.1 BASIC ASSUMPTION OF LINEAR ANALYSIS 20 2.3.2 NOISE SOURCES OF AD-PLL 21 2.3.3 EFFECTS OF LOOP DELAY ON AD-PLL 24 2.3.4 PHASE NOISE ANALYSIS OF PROPOSED AD-PLL 26 CHAPTER 3 DESIGN OF ALL-DIGITAL PLL 28 3.1 DESIGN CONSIDERATION 28 3.2 OVERALL ARCHITECTURE 30 3.3 CIRCUIT IMPLEMENTATION 32 3.3.1 PFD-TDC 32 3.3.2 DCO 37 3.3.3 DIGITAL BLOCK 43 3.3.4 LEVEL SHIFTING BUFFER AND DIVIDER 45 CHAPTER 4 MEASUREMENT AND SIMULATION RESULTS 52 4.1 DIE PHOTOMICROGRAPH 52 4.2 MEASUREMENT SETUP 54 4.3 TRANSIENT ANALYSIS 57 4.4 PHASE NOISE AND SPUR PERFORMANCE 59 4.4.1 FREE-RUNNING DCO 59 4.4.2 PLL PERFORMANCE 61 4.5 PERFORMANCE SUMMARY 65 CHAPTER 5 CONCLUSION 67 BIBLIOGRAPHY 68 ์ดˆ ๋ก 72Maste

    ๋‹ค์ด๋ ‰ํŠธ ๊ฒฝ๋กœ๋ฅผ ์ด์šฉํ•œ 5/8GHz ๋“€์–ผ ๋ชจ๋“œ All-Digital Phase-Locked Loop์˜ ์„ค๊ณ„

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    ํ•™์œ„๋…ผ๋ฌธ (์„์‚ฌ)-- ์„œ์šธ๋Œ€ํ•™๊ต ๋Œ€ํ•™์› : ๊ณต๊ณผ๋Œ€ํ•™ ์ „๊ธฐยท์ •๋ณด๊ณตํ•™๋ถ€, 2019. 2. ์ •๋•๊ท .์ตœ๊ทผ ๋ฐ์ดํ„ฐ์˜ ์ „์†ก ์†๋„๊ฐ€ ๋น„์•ฝ์ ์œผ๋กœ ์ฆ๊ฐ€ํ•จ์— ๋”ฐ๋ผ ๋ฐ์ดํ„ฐ ์ฒ˜๋ฆฌ ๋ฐฉ์‹์ด ๋‹ค์–‘ํ•˜๊ฒŒ ์—ฐ๊ตฌ๋˜์—ˆ๊ณ  ์—ฌ๋Ÿฌ ๋ฐฉ์‹์— ๋”ฐ๋ฅธ ๊ณ ์†์˜ ์†ก์ˆ˜์‹ ๊ธฐ ์„ค๊ณ„๊ฐ€ ์ค‘์š”์‹œ๋˜๊ณ  ์žˆ๋‹ค. ๊ทธ ์ค‘์—์„œ๋„ Clock ์‹ ํ˜ธ๋ฅผ ํ•ฉ์„ฑํ•˜๋Š” ์—ญํ• ์ธ Phase-Locked Loop (PLL)์— ๋Œ€ํ•œ ์—ฐ๊ตฌ๊ฐ€ ํ™œ๋ฐœํžˆ ์ง„ํ–‰๋˜๊ณ  ์žˆ๋‹ค. ํŠนํžˆ ํŒจ์‹œ๋ธŒ ์†Œ์ž๋ฅผ Loop Filter์— ์‚ฌ์šฉํ•ด์•ผ ํ•˜๋Š” Analog PLL๋ณด๋‹ค๋Š” PVT ๋ณ€ํ™”์— ๋‘”๊ฐํ•˜๊ณ  Programmable ํ•˜๋‹ค๋Š” ์žฅ์ ์„ ๊ฐ€์ง„ All Digital PLL (AD-PLL)์— ๋Œ€ํ•œ ๊ด€์‹ฌ๋„๊ฐ€ ๋†’์•„์ง€๊ณ  ์žˆ๋‹ค. ๋ณธ ๋…ผ๋ฌธ์—์„œ๋Š” Peripheral Component Interconnect Express Memory interface (PCIe) ์ง€์›์„ ์œ„ํ•œ 32Gbps Serial Link์— Common Clock ์‹ ํ˜ธ๋ฅผ ์ œ๊ณตํ•˜๋Š” 5/8 GHz ๋“€์–ผ ๋ชจ๋“œ AD-PLL์„ ์ œ์•ˆํ•œ๋‹ค. ์ด์ „ ์„ธ๋Œ€์™€์˜ ํ˜ธํ™˜์„ฑ์„ ์œ„ํ•ด ๋„“์€ ๋™์ž‘ ์˜์—ญ์„ ๊ฐ–๊ณ  ๋ชจ๋“œ ์„ ํƒ์ด ๊ฐ€๋Šฅํ•œ ๋“€์–ผ ๋ชจ๋“œ Digitally Controlled Oscillator (DCO)๋ฅผ ์‚ฌ์šฉํ•˜์˜€๊ณ  ์„ค๊ณ„ ์ „ Digital ๋ฐฉ์‹์œผ๋กœ ๋ณ€ํ™˜ํ•จ์— ๋”ฐ๋ผ ๋ฐœ์ƒํ•˜๋Š” Quantization Noise์— ๋Œ€ํ•ด ๋ถ„์„ํ•˜๊ณ  Matlab, Verilog Behavioral Simulation์„ ํ†ตํ•ด ์ถœ๋ ฅ์˜ Phase Noise์™€ RMS Jitter ๊ฐ’์„ ์˜ˆ์ธกํ•ด ๋ณผ ์ˆ˜ ์žˆ์—ˆ๋‹ค. ๋˜ํ•œ Reference Clock์˜ ํ•œ ์ฃผ๊ธฐ ์ด๋‚ด์— ์ •๋ณด๊ฐ€ Update๋˜์ง€ ๋ชปํ•˜๋Š” Loop Delay์˜ ๋ฌธ์ œ๋ฅผ ํ•ด๊ฒฐํ•˜๊ธฐ ์œ„ํ•ด Digital Loop Filter (DLF)์˜ ์ฒ˜๋ฆฌ ๊ณผ์ •์„ ๊ฑฐ์น˜์ง€ ์•Š๊ณ  Time to Digital Converter (TDC)์˜ ์ถœ๋ ฅ์„ DCO์— ๋ฐ”๋กœ ์ „๋‹ฌํ•ด ์ค„ ์ˆ˜ ์žˆ๋Š” ๋‹ค์ด๋ ‰ํŠธ ๊ฒฝ๋กœ๋ฅผ ์ œ์•ˆํ•˜์˜€๋‹ค. ์„ค๊ณ„๋œ ํšŒ๋กœ๋Š” TSMC ์‚ฌ์˜ 65nm ๊ณต์ •์œผ๋กœ ๊ตฌํ˜„๋˜์—ˆ๊ณ  AD-PLL์˜ ์ „์ฒด ์œ ํšจ ๋ฉด์ ์€ Decoupling Cap์„ ์ œ์™ธํ•˜๊ณ  420umยท300um์ด๋ฉฐ ์ธก์ •๋œ ์ถœ๋ ฅ Clock ์‹ ํ˜ธ์˜ RMS Jitter๊ฐ’์€ 8GHz ๋ชจ๋“œ์—์„œ 357fs, 5GHz ๋ชจ๋“œ์—์„œ 394fs์ด๋‹ค. AD-PLL์˜ ๋™์ž‘ ์ฃผํŒŒ์ˆ˜๋Š” PCIe Spec์˜ ๋‹ค์–‘ํ•œ ๋ชจ๋“œ๋ฅผ ์ง€์›ํ•˜๊ธฐ ์œ„ํ•ด ์™ธ๋ถ€์˜ ์ž…๋ ฅ ๋ชจ๋“œ ์‹ ํ˜ธ์— ๋”ฐ๋ผ์„œ 5GHz/8GHz์˜ High/Low Band๋ฅผ ์ง€์›ํ•˜๊ณ  1.2V์˜ ๊ณต๊ธ‰ ์ „์••์—์„œ Repeater๋ฅผ ์ œ์™ธํ•˜๊ณ  8GHz ๋ชจ๋“œ์—์„œ๋Š” ์ด 18.26mW, 5GHz ๋ชจ๋“œ์—์„œ๋Š” ์ด 12.06mW์˜ Power๋ฅผ ์†Œ๋น„ํ•œ๋‹ค.As data transmission speed has increased in recent years, a variety of data processing techniques have been studied and high-speed transceiver has become important. Above all, Phase-Locked Loop (PLL), which synthesizes high frequency clock signal, is one of the important parts. In particular, All-Digital PLL(AD-PLL), which has advantage of programmability and PVT tolerance, is replacing Analog PLL that requires passive element utilization. This thesis presents a 5/8GHz dual mode AD-PLL to provide common clock signal to 32Gbps serial link to support Peripheral Component Interconnect Express(PCIe) PHY. For compatibility with previous generations and wide operating region, AD-PLL uses dual mode Digitally Controlled Oscillator(DCO). Before an actual design, output RMS Jitter, Phase Noise of AD-PLL and quantization error resulting from digital conversion are calculated and analyzed by using Matlab, Verilog behavioral simulation in a short time. In addition, the output of Time-to-Digital Converter(TDC) is directly delivered to the DCO without Digital Loop Filter(DLF) using direct path to solve loop delay issue where information cant be updated within a cycle of reference clock. The proposed AD-PLL is fabricated in 65nm CMOS process and effective area of AD-PLL is 420umยท300um and the measured RMS Jitter is 357fs at 8GHz mode, 394fs at 5GHz mode. Also, proposed AD-PLL supports the low/high band(5/8GHz) to be compatible with the various modes of PCIe spec. Power dissipation is 18.26mW at 8GHz mode, 12.06mW at 5GHz mode in 1.2V supply voltage domain excluding repeater.์ œ 1 ์žฅ ์„œ ๋ก  1 1.1 ์—ฐ๊ตฌ์˜ ๋ฐฐ๊ฒฝ 1 1.2 ๋…ผ๋ฌธ์˜ ๊ตฌ์„ฑ 3 ์ œ 2 ์žฅ Basics of AD-PLL 4 2.1 Introduction of AD-PLL 4 2.2 Building Blocks of AD-PLL 5 2.2.1 Time to Digital Converter 6 2.2.2 Digital Loop Filter 8 2.2.3 Digitally Controlled Oscillator 10 2.3 Phase Noise Analysis 13 2.4 Loop Delay 18 ์ œ 3 ์žฅ Design of AD-PLL 22 3.1 Design Consideration 22 3.2 Overall Architecture 22 3.3 Phase Frequency Detectable TDC 24 3.4 Digital Loop Filter 27 3.5 Digitally Controlled Oscillator 30 3.6 Direct Path 33 3.7 Level Shifter and Divider 36 3.8 Clock Tree 39 ์ œ 4 ์žฅ Measurement and Simulation Results 41 4.1 Measurement Setup 41 4.2 Die Photomicrograph 43 4.3 Frequency Tracking Behavior 44 4.4 Clock Distribution 46 4.5 Phase Noise and Spur 47 4.6 Performance Summary 53 ์ œ 5 ์žฅ Conclusion 55 ์ฐธ๊ณ  ๋ฌธํ—Œ 56 Abstract 59Maste

    Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator

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