Design of a tunable multi-band differential LC VCO using 0.35 mu m SiGe BiCMOS technology for multi-standard wireless communication systems

In this paper, an integrated 2.2-5.7GHz multi-band differential LC VCO for multi-standard wireless communication systems was designed utilizing 0.35 mu m SiGe BiCMOS technology. The topology, which combines the switching inductors and capacitors together in the same circuit, is a novel approach for wideband VCOs. Based on the post-layout simulation results, the VCO can be tuned using a DC voltage of 0 to 3.3 V for 5 different frequency bands (2.27-2.51 GHz, 2.48-2.78 GHz, 3.22-3.53 GHz, 3.48-3.91 GHz and 4.528-5.7 GHz) with a maximum bandwidth of 1.36 GHz and a minimum bandwidth of 300 MHz. The designed and simulated VCO can generate a differential output power between 0.992 and -6.087 dBm with an average power consumption of 44.21 mW including the buffers. The average second and third harmonics level were obtained as -37.21 and -47.6 dBm, respectively. The phase noise between -110.45 and -122.5 dBc/Hz, that was simulated at 1 MHz offset, can be obtained through the frequency of interest. Additionally, the figure of merit (FOM), that includes all important parameters such as the phase noise, the power consumption and the ratio of the operating frequency to the offset frequency, is between -176.48 and -181.16 and comparable or better than the ones with the other current VCOs. The main advantage of this study in comparison with the other VCOs, is covering 5 frequency bands starting from 2.27 up to 5.76 GHz without FOM and area abandonment. Output power of the fundamental frequency changes between -6.087 and 0.992 dBm, depending on the bias conditions (operating bands). Based on the post-layout simulation results, the core VCO circuit draws a current between 2.4-6.3 mA and between 11.4 and 15.3 mA with the buffer circuit from 3.3 V supply. The circuit occupies an area of 1.477 mm(2) on Si substrate, including DC, digital and RF pads

LC-VCO design optimization methodology based on the gm/ID ratio for nanometer CMOS technologies

In this paper, an LC voltage-controlled oscillator (LC-VCO) design optimization methodology based on the gm/ID technique and on the exploration of all inversion regions of the MOS transistor (MOST) is presented. An in-depth study of the compromises between phase noise and current consumption permits optimization of the design for given specifications. Semiempirical models of MOSTs and inductors, obtained by simulation, jointly with analytical phase noise models, allow to get a design space map where the design tradeoffs are easily identified. Four LC-VCO designs in different inversion regions in a 90-nm CMOS process are obtained with the proposed methodology and verified with electrical simulations. Finally, the implementation and measurements are presented for a 2.4-GHz VCO operating in moderate inversion. The designed VCO draws 440 μA from a 1.2-V power supply and presents a phase noise of -106.2 dBc/Hz at 400 kHz from the carrier

Long-term Stabilization of Fiber Laser Using Phase-locking Technique with Ultra-low Phase Noise and Phase Drift

We review the conventional phase-locking technique in the long-term stabilization of the mode-locked fiber laser and investigate the phase noise limitation of the conventional technique. To break the limitation, we propose an improved phase-locking technique with an optic-microwave phase detector in achieving the ultra-low phase noise and phase drift. The mechanism and the theoretical model of the novel phase-locking technique are also discussed. The long-term stabilization experiments demonstrate that the improved technique can achieve the long-term stabilization for the MLFL with ultra-low phase noise and phase drift. The excellent locking performance of the improved phase-locking technique implies that this technique can be used to stabilize the mode-locked fiber laser with the highly stable H-master or optical clock without stability loss

Hybrid Millimeter-Wave Systems: A Novel Paradigm for HetNets

Heterogeneous Networks (HetNets) are known to enhance the bandwidth efficiency and throughput of wireless networks by more effectively utilizing the network resources. However, the higher density of users and access points in HetNets introduces significant inter-user interference that needs to be mitigated through complex and sophisticated interference cancellation schemes. Moreover, due to significant channel attenuation and presence of hardware impairments, e.g., phase noise and amplifier nonlinearities, the vast bandwidth in the millimeter-wave band has not been fully utilized to date. In order to enable the development of multi-Gigabit per second wireless networks, we introduce a novel millimeter-wave HetNet paradigm, termed hybrid HetNet, which exploits the vast bandwidth and propagation characteristics in the 60 GHz and 70-80 GHz bands to reduce the impact of interference in HetNets. Simulation results are presented to illustrate the performance advantage of hybrid HetNets with respect to traditional networks. Next, two specific transceiver structures that enable hand-offs from the 60 GHz band, i.e., the V-band to the 70-80 GHz band, i.e., the E-band, and vice versa are proposed. Finally, the practical and regulatory challenges for establishing a hybrid HetNet are outlined.Comment: 12 pages, 5 Figures, IEEE Communication Magazine. In pres

Design of a 4.2-5.4 GHz differential LC VCO using 0.35 mu m SiGeBiCMOS technology for IEEE 802.11a applications

In this paper, a 4.2-5.4 GHz, -Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35 mu m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). According to post-layout simulation results, phase noise is -110.7 dBc/Hz at 1 MHz offset from 5.4 GHz carrier frequency and -113.4 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained from the simulations, utilizing accumulation-mode varactors. Phase noise was also found to be relatively low because of taking advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. Based on the simulation results, the circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit layout occupies an area of 0.6 mm(2) on Si substrate, including DC and RF pads

High Current Matching over Full-Swing and Low-Glitch Charge Pump Circuit for PLLs

A high current matching over full-swing and low-glitch charge pump (CP) circuit is proposed. The current of the CP is split into two identical branches having one-half the original current. The two branches are connected in source-coupled structure, and a two-stage amplifier is used to regulate the common-source voltage for the minimum current mismatch. The proposed CP is designed in TSMC 0.18µm CMOS technology with a power supply of 1.8 V. SpectreRF based simulation results show the mismatch between the current source and the current sink is less than 0.1% while the current is 40 µA and output swing is 1.32 V ranging from 0.2 V to 1.52 V. Moreover, the transient output current presents nearly no glitches. The simulation results verify the usage of the CP in PLLs with the maximum tuning range from the voltage-controlled oscillator, as well as the low power supply applications

Optical Phase Locking techniques: an overview and a novel method based on Single Side Sub-Carrier modulation

A short overview on Optical Phase locking techniques and a detailed description of the Phase Locking technique based on Sub-Carriers modulation is presented. Furthermore, a novel Single Side Sub-Carrierbased Optical Phase Locked Loop (SS-SC-OPLL), with off the shelf optical components, is also presented and experimentally demonstrated. Our new method, based on continuous wave semiconductor lasers and optical single side sub-carrier modulation using QPSK LiNbO3 modulator, allows a practical implementation with better performance with respect to the previously proposed OPLL circuits, and permits an easy use in real time WDM signal coherent demodulation