Custom Integrated Circuits

Contains reports on ten research projects.Analog Devices, Inc.IBM CorporationNational Science Foundation/Defense Advanced Research Projects Agency Grant MIP 88-14612Analog Devices Career Development Assistant ProfessorshipU.S. Navy - Office of Naval Research Contract N0014-87-K-0825AT&TDigital Equipment CorporationNational Science Foundation Grant MIP 88-5876

A Two-Tiered Correlation of Dark Matter with Missing Transverse Energy: Reconstructing the Lightest Supersymmetric Particle Mass at the LHC

We suggest that non-trivial correlations between the dark matter particle mass and collider based probes of missing transverse energy H_T^miss may facilitate a two tiered approach to the initial discovery of supersymmetry and the subsequent reconstruction of the LSP mass at the LHC. These correlations are demonstrated via extensive Monte Carlo simulation of seventeen benchmark models, each sampled at five distinct LHC center-of-mass beam energies, spanning the parameter space of No-Scale F-SU(5).This construction is defined in turn by the union of the Flipped SU(5) Grand Unified Theory, two pairs of hypothetical TeV scale vector-like supersymmetric multiplets with origins in F-theory, and the dynamically established boundary conditions of No-Scale Supergravity. In addition, we consider a control sample comprised of a standard minimal Supergravity benchmark point. Led by a striking similarity between the H_T^miss distribution and the familiar power spectrum of a black body radiator at various temperatures, we implement a broad empirical fit of our simulation against a Poisson distribution ansatz. We advance the resulting fit as a theoretical blueprint for deducing the mass of the LSP, utilizing only the missing transverse energy in a statistical sampling of >= 9 jet events. Cumulative uncertainties central to the method subsist at a satisfactory 12-15% level. The fact that supersymmetric particle spectrum of No-Scale F-SU(5) has thrived the withering onslaught of early LHC data that is steadily decimating the Constrained Minimal Supersymmetric Standard Model and minimal Supergravity parameter spaces is a prime motivation for augmenting more conventional LSP search methodologies with the presently proposed alternative.Comment: JHEP version, 17 pages, 9 Figures, 2 Table

An Integrated Test Plan for an Advanced Very Large Scale Integrated Circuit Design Group

VLSI testing poses a number of problems which includes the selection of test techniques, the determination of acceptable fault coverage levels, and test vector generation. Available device test techniques are examined and compared. Design rules should be employed to assure the design is testable. Logic simulation systems and available test utilities are compared. The various methods of test vector generation are also examined. The selection criteria for test techniques are identified. A table of proposed design rules is included. Testability measurement utilities can be used to statistically predict the test generation effort. Field reject rates and fault coverage are statistically related. Acceptable field reject rates can be achieved with less than full test vector fault coverage. The methods and techniques which are examined form the basis of the recommended integrated test plan. The methods of automatic test vector generation are relatively primitive but are improving

Cost modelling and concurrent engineering for testable design

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.As integrated circuits and printed circuit boards increase in complexity, testing becomes a major cost factor of the design and production of the complex devices. Testability has to be considered during the design of complex electronic systems, and automatic test systems have to be used in order to facilitate the test. This fact is now widely accepted in industry. Both design for testability and the usage of automatic test systems aim at reducing the cost of production testing or, sometimes, making it possible at all. Many design for testability methods and test systems are available which can be configured into a production test strategy, in order to achieve high quality of the final product. The designer has to select from the various options for creating a test strategy, by maximising the quality and minimising the total cost for the electronic system. This thesis presents a methodology for test strategy generation which is based on consideration of the economics during the life cycle of the electronic system. This methodology is a concurrent engineering approach which takes into account all effects of a test strategy on the electronic system during its life cycle by evaluating its related cost. This objective methodology is used in an original test strategy planning advisory system, which allows for test strategy planning for VLSI circuits as well as for digital electronic systems. The cost models which are used for evaluating the economics of test strategies are described in detail and the test strategy planning system is presented. A methodology for making decisions which are based on estimated costing data is presented. Results of using the cost models and the test strategy planning system for evaluating the economics of test strategies for selected industrial designs are presented

What is the Path to Fast Fault Simulation?

Motivated by the recent advances in fast fault simulation techniques for large combinational circuits, a panel discussion has been organized for the 1988 International Test Conference. This paper is a collective account of the position statements offered by the panelists

Quiescent current testing of CMOS data converters

Power supply quiescent current (IDDQ) testing has been very effective in VLSI circuits designed in CMOS processes detecting physical defects such as open and shorts and bridging defects. However, in sub-micron VLSI circuits, IDDQ is masked by the increased subthreshold (leakage) current of MOSFETs affecting the efficiency of I¬DDQ testing. In this work, an attempt has been made to perform robust IDDQ testing in presence of increased leakage current by suitably modifying some of the test methods normally used in industry. Digital CMOS integrated circuits have been tested successfully using IDDQ and IDDQ methods for physical defects. However, testing of analog circuits is still a problem due to variation in design from one specific application to other. The increased leakage current further complicates not only the design but also testing. Mixed-signal integrated circuits such as the data converters are even more difficult to test because both analog and digital functions are built on the same substrate. We have re-examined both IDDQ and IDDQ methods of testing digital CMOS VLSI circuits and added features to minimize the influence of leakage current. We have designed built-in current sensors (BICS) for on-chip testing of analog and mixed-signal integrated circuits. We have also combined quiescent current testing with oscillation and transient current test techniques to map large number of manufacturing defects on a chip. In testing, we have used a simple method of injecting faults simulating manufacturing defects invented in our VLSI research group. We present design and testing of analog and mixed-signal integrated circuits with on-chip BICS such as an operational amplifier, 12-bit charge scaling architecture based digital-to-analog converter (DAC), 12-bit recycling architecture based analog-to-digital converter (ADC) and operational amplifier with floating gate inputs. The designed circuits are fabricated in 0.5 μm and 1.5 μm n-well CMOS processes and tested. Experimentally observed results of the fabricated devices are compared with simulations from SPICE using MOS level 3 and BSIM3.1 model parameters for 1.5 μm and 0.5 μm n-well CMOS technologies, respectively. We have also explored the possibility of using noise in VLSI circuits for testing defects and present the method we have developed

Developing a Methodology to Detect Partial Failures for Dynamic Systems

The purpose of this research is to develop a decision support system that can assist in detecting partial failures in dynamic systems such as Fire Control System Tracking Radar (TR) onboard Naval Ships. Partial failures do not necessarily shut down the system immediately but cause degradation of operational performance. Previous work has shown that experts in the field of failure detection, test point insertion and Built-In-Test Equipment (BITE) can provide useful input in detecting partial failures. Partial failures affect operational system performance and support costs, which can be significant. Often, however, partial failure detection consists of the estimations and opinions of the experts. This has not been addressed adequately in the literature. It is postulated that the approach developed in this research could be applied to maintain and monitor partial failure. The development of such a testing aid is the thrust of this research effort. Markov chains, k-out-of-n: G: system and critical path tracing techniques, among others are employed. Appropriate survey questionnaires are used for validation of the resulting test model. Application of previous test point insertion techniques are applied as a part of system comparison and assessment