UVM Based Verification of CAN Protocol Controller Using System Verilog

Over the years, design complexity and size have stubbornly obeyed the growth curve predicted by Gordon Moore. The industry is migrating towards leading edge nodes, which can hold more than 100 Million gates. The chip makers want to pack as many functions possible in their SoCs and provide as many feature additions to gain market share. And, of course, all of those features need to be verified. Verification is currently the largest challenge facing the semiconductor industry in keeping pace with both the customer demand for features and our technical ability to add millions of gates to our chips. Verification quality is a must for functional safety in electronic systems. This paper describes the verification of CAN Protocol Controller using System Verilog. The CAN Controller functions as the interface between an application and the actual CAN bus. Taking this need in consideration, this paper describes flow from specification extraction to development of verification environment. DOI: 10.17762/ijritcc2321-8169.15058

Development of UVM based Reusabe Verification Environment for SHA-3 Cryptographic Core

In this work, an industry standard methodology for ASIC verification domain, SystemVerilog (SV) with Universal Verification Methodology (UVM) is introduced with its features and application to Keccak SHA-3 Cryptographic Core. The ASIC verification flow for SHA-3 core is followed with creation of UVM based verification environment. By application of UVM on the core, horizontal and vertical re-use can be achieved in standard projects. Proposed verification environment uses OOPs concepts from SV UVM to develop layered testbench. In this approach initial learning curve is slow, considering overhead to learn new verification methodology. But, once full fledge working environment is created, re-usability feature from SV UVM can be achieved with less amount of time. Also coverage results give effectiveness of the proposed verification environment. DOI: 10.17762/ijritcc2321-8169.15057

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared.Comment: 15 pages, 10 figures (11 figure files), submitted to Journal of Instrumentatio

Analyzing UVM reuse

Abstract. This thesis investigates Universal Verification Methodology’s (UVM) reuse possibilities. Initally, the object-oriented features of the UVM’s programming language SystemVerilog (SV), are introduced. Those features are one enabling factor in UVM reuse. The work also provides a brief overview to the development history of UVM and presents its properties. The structure of a conventional UVM testbench is also demonstrated. Finally, the features that make the UVM testbench more reusable are briefly introduced. In the practical part of the study, a UVM testbench is made for Nordic Semiconductor’s Introproject. The testbench was created with extensive comments so that beginners would get the most out of it. The methods that make the testbench reusable are also applied to the testbench. At the end of the practical part, the reuse possibilities of the testbench were tested by changing the Design Under Test (DUT). Modifications were made to the testbench in order to match the new features of the DUT.UVM uudelleenkäytön analysointi. Tiivistelmä. Tämä diplomityö tutkii Universaalin varmennusmenetelmän (UVM) uudelleenkäyttömahdollisuuksia. Aluksi UVM:n ohjelmointikielen, SystemVerilogin olio-ohjelmointipohjaisia ominaisuuksia käydään läpi. Nämä ominaisuudet ovat yksi mahdollistava tekijä UVM uudelleenkäytössä. Työssä tehdään lisäksi lyhyt katsaus UVM:n kehityshistoriaan ja esitellään myös sen ominaisuudet sekä tavanomaisen UVM-testipenkin rakenne. Lopuksi esitellään lyhyesti ominaisuuksia, jolla saa tehtyä UVM testipenkistä paremmin uudelleenkäytettävän. Työn käytännön osuudessa tehdään UVM-testipenkki Nordic Semiconductorin Introprojektiin. Testipenkki tehtiin laajasti kommentoimalla, jotta aloitteleva testipenkin tekijä saa siitä mahdollisimman paljon irti. Testipenkin tekemisessä käytettiin myös menetelmiä, joita esiteltiin aiemmassa teoriakappaleessa. Käytännön osuuden lopuksi testattiin testipenkin uudelleenkäyttöä muuttamalla testissä olevaa komponenttia. Testipenkkiin tehtiin muutokset, jolla se saatiin taas vastaamaan komponentin tarpeita