Bit-level Parallelization of 3DES Encryption on GPU

Triple DES (3DES) is a standard fundamental encryption algorithm, used in several electronic payment applications and web browsers. In this paper, we propose a parallel implementation of 3DES on GPU. Since 3DES encrypts data with 64-bit blocks, our approach considers each 64-bit block a kernel block and assign a separate thread to process each bit. Algorithm's permutation operations, XOR operations, and S-box operations are done in parallel within these kernel blocks. The implementation benefits from the use of constant and shared memory types to optimize memory access. The results show an average 10.70x speed-up against the baseline multi-threaded CPU implementation. The implementation is publicly available at https://github.com/kaanfurkan35/3DES_GP

Towards Designing Energy Efficient Symmetric Key Protocols

Energy consumption by various modern symmetric key encryption protocols (DES, 3-DES, AES and, Blowfish) is studied from an algorithmic perspective. The work is directed towards redesigning or modifying the underlying algorithms for these protocols to make them consume less energy than they currently do. This research takes the approach of reducing energy consumption by parallelizing the consecutive memory accesses of symmetric key encryption algorithms. To achieve parallelization, an existing energy complexity model is applied to symmetric key encryption algorithms. Inspired by the popular DDR3 architecture, the model assumes that main memory is divided into multiple banks, each of which can store multiple blocks. Each block in a bank can only be accessed from a cache of its own, that can hold exactly one block. However all the caches from different banks can be accessed simultaneously. In this research, experiments are conducted to measure the difference in energy consumption by varying the level of parallelization, i.e. variations of, number of banks that can be accessed in parallel. The experimental results show that the higher the level of parallelism, smaller is the energy consumption

Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard) algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array) embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication

Improving Hardware Implementation of Cryptographic AES Algorithm and the Block Cipher Modes of Operation

With ever increasing Internet traffic, more business and financial transactions are being conducted online. This is even more so during these days of COVID-19 pandemic when traditional businesses such as traditional face to face educational systems have gone online requiring huge amount of data being exchanged over Internet. Increase in the volume of data sent over the Internet has also increased the security vulnerabilities such as challenging the confidentiality of data being sent over the Internet. Due to sheer volume, all data will need to be effectively encrypted. Due to increase in the volume of data, it is also important to have encryption/decryption functions to work at a higher speed to maintain the confidentiality of sensitive data. In this thesis, our goal is to enhance the hardware speed of encryption process of the standard AES scheme and its four variants such as AES-128, AES-192, AES-256 and new AES-512 and implement such functions on an FPGA. We also consider the FPGA implementation of different modes of AES operation. By employing parallelism and pipelining approach, we attempt to speed up various computational components of AES implementations using the Quartus II onto Intel’s FPGA. This approach shows improvement in the response speed, data throughput and latency

PIPELINED DATA PARALLEL MODEL OF ADVANCED ENCRYPTION STANDARD ALGORITHM

The Advanced Encryption Standard (AES) was officially adopted in 2002 as the new encryption standard algorithm. AES specifies a FIPS-approved cryptographic algorithm that can be used to protect electronic data. It is a symmetric block cipher that can encrypt and decrypt information. This paper develops a pipelined data parallel model of AES. The parallelism in the algorithm is two dimensional. The first dimension is AES enter-stage (pipelining) and the second dimension is data parallelism. Pipelining parallelism exploits the availability of several processes to execute different stages of different data blocks in parallel. The data parallelism exploits data independence among data blocks to implement data level parallelism. The parallel implementation of AES decreases the time needed for encryption and decryption processes. We use the ECB mode in encryption/decryption algorithm in our parallel implementation of AES to implement the parallelization at data level where data blocks are encrypted and decrypted in parallel. We also develop an MPI-based algorithm to be used with a cluster of workstations (COW). We validate the approach by simulating the model with various input parameters (input data file size, number of processes, communication/computation operation execution time, etc.) and measuring the corresponding performance. Performance metrics include speedup, communication to computation ratio and efficiency. Results show that performance obtained by the developed model is superior to parallel implementations of AES which include only data parallelism or pipelining