Programming Languages for Data-Intensive HPC Applications: a Systematic Mapping Study

A major challenge in modelling and simulation is the need to combine expertise in both software technologies and a given scientific domain. When High-Performance Computing (HPC) is required to solve a scientific problem, software development becomes a problematic issue. Considering the complexity of the software for HPC, it is useful to identify programming languages that can be used to alleviate this issue. Because the existing literature on the topic of HPC is very dispersed, we performed a Systematic Mapping Study (SMS) in the context of the European COST Action cHiPSet. This literature study maps characteristics of various programming languages for data-intensive HPC applications, including category, typical user profiles, effectiveness, and type of articles. We organised the SMS in two phases. In the first phase, relevant articles are identified employing an automated keyword-based search in eight digital libraries. This lead to an initial sample of 420 papers, which was then narrowed down in a second phase by human inspection of article abstracts, titles and keywords to 152 relevant articles published in the period 2006–2018. The analysis of these articles enabled us to identify 26 programming languages referred to in 33 of relevant articles. We compared the outcome of the mapping study with results of our questionnaire-based survey that involved 57 HPC experts. The mapping study and the survey revealed that the desired features of programming languages for data-intensive HPC applications are portability, performance and usability. Furthermore, we observed that the majority of the programming languages used in the context of data-intensive HPC applications are text-based general-purpose programming languages. Typically these have a steep learning curve, which makes them difficult to adopt. We believe that the outcome of this study will inspire future research and development in programming languages for data-intensive HPC applications.Additional co-authors: Sabri Pllana, Ana Respício, José Simão, Luís Veiga, Ari Vis

Uma avaliação experimental da plataforma parallella utilizando controle preditivo baseado em modelo como um estudo de caso

Dissertação (mestrado)—Universidade de Brasília, Faculdade de Tecnologia, Departamento de Engenharia Mecânica, 2017.Nas últimas décadas, o poder computacional de sistemas embarcados têm crescido de forma muito rápida. Em geral, tais sistema são projetados para operar sob restrições como portabilidade (peso e tamanho), consumo de recursos, baixo consumo de energia e dissipação de potência. Assim, motivado pelos fatores supracitados e pelo avanço tecnológico, assim como pela demanda crescente de desempenho por parte das aplicações embarcadas, têm surgido vários processadores e plataformas de hardware que fazem uso de arquiteturas multicore, com destaque para a Parallella, uma plataforma de alto desempenho e baixo consumo energético. Nesse sentido, o presente trabalho traz a proposta de se avaliar tal plataforma sob uma abordagem experimental, como foco em seu coprocessador Epiphany de 16 cores, quando utilizada como um acelerador em software para aplicações de controle preditivo baseado em modelo como um estudo de caso, devido sua relevância para o grupo de pesquisa do LEIA (Laboratório de Sistemas Embarcados e Aplicações de Circuitos Integrados – Universidade de Brasília). Os resultados mostram que, apesar de restrições críticas como o tamanho da memória local dos cores, a plataforma Parallella se apresenta como uma arquitetura em potencial, podendo ser vista como uma alternativa à aceleração de algoritmos em hardware. Melhorias futuras como a expansão do número de núcleos do MPSoC Epiphany e da memória local dos mesmos, como previsto pelos fundadores do projeto, poderão alavancar ainda mais o uso de tal arquitetura em aplicações embarcadas.In the last decades, the computational power of embedded systems has grown very fast. In general, such systems are designed to operate under constraints such as portability, resource consumption, low power consumption and power dissipation. Thus, due to the aforementioned factors and technological advances, as well as the increasing demand for performance by embedded applications, there have been several processors and hardware platforms that make use of multicore architectures, with emphasis on a Parallella, a platform of high performance and low consumption. In this sense, the present work presents a proposal to evaluate such platform in an experimental approach, focusing on its Epiphany 16-core co-processor, when used as a software accelerator for model-based predictive control applications as a case study, due to its relevance to the research group of LEIA (Laboratory of Embedded Systems and Applications of Integrated Circuits - University of Brasilia). The results show that, despite critical constraints such as the local memory size of the cores, a Parallella platform presents itself as a potential architecture and can be seen as an alternative to accelerating hardware algorithms. Future improvements such as the expansion of the number of MPSoC Epiphany cores and their local memory, as predicted by the founders of the project, can leverage the use of this architecture in embedded application