Dielectric breakdown II: Related projects at the University of Twente

In this paper an overview is given of the related activities in our group of the University of Twente. These are on thin film transistors with the inherent difficulty of making a gate dielectric at low temperature, on thin dielectrics for EEPROM devices with well-known requirements with respect to charge retention and endurance and, finally, on thin film diodes in displays with unexpected breakdown properties

Dielectric breakdown I: A review of oxide breakdown

This paper gives an overview of the dielectric breakdown in thin oxide layers on silicon. First test methods are discussed, followed by their application to the estimation of the oxide lifetime. The main part of the paper is devoted to the physical background of the intrinsic breakdown. Finally, defect-related or extrinsic breakdown is discussed

ELECTRICAL CHARACTERIZATION, PHYSICS, MODELING AND RELIABILITY OF INNOVATIVE NON-VOLATILE MEMORIES

Enclosed in this thesis work it can be found the results of a three years long research activity performed during the XXIV-th cycle of the Ph.D. school in Engineering Science of the Università degli Studi di Ferrara. The topic of this work is concerned about the electrical characterization, physics, modeling and reliability of innovative non-volatile memories, addressing most of the proposed alternative to the floating-gate based memories which currently are facing a technology dead end. Throughout the chapters of this thesis it will be provided a detailed characterization of the envisioned replacements for the common NOR and NAND Flash technologies into the near future embedded and MPSoCs (Multi Processing System on Chip) systems. In Chapter 1 it will be introduced the non-volatile memory technology with direct reference on nowadays Flash mainstream, providing indications and comments on why the system designers should be forced to change the approach to new memory concepts. In Chapter 2 it will be presented one of the most studied post-floating gate memory technology for MPSoCs: the Phase Change Memory. The results of an extensive electrical characterization performed on these devices led to important discoveries such as the kinematics of the erase operation and potential reliability threats in memory operations. A modeling framework has been developed to support the experimental results and to validate them on projected scaled technology. In Chapter 3 an embedded memory for automotive environment will be shown: the SimpleEE p-channel memory. The characterization of this memory proven the technology robustness providing at the same time new insights on the erratic bits phenomenon largely studied on NOR and NAND counterparts. Chapter 4 will show the research studies performed on a memory device based on the Nano-MEMS concept. This particular memory generation proves to be integrated in very harsh environment such as military applications, geothermal and space avionics. A detailed study on the physical principles underlying this memory will be presented. In Chapter 5 a successor of the standard NAND Flash will be analyzed: the Charge Trapping NAND. This kind of memory shares the same principles of the traditional floating gate technology except for the storage medium which now has been substituted by a discrete nature storage (i.e. silicon nitride traps). The conclusions and the results summary for each memory technology will be provided in Chapter 6. Finally, on Appendix A it will be shown the results of a recently started research activity on the high level reliability memory management exploiting the results of the studies for Phase Change Memories

Feasibility of self-structured current accessed bubble devices in spacecraft recording systems

The self-structured, current aperture approach to magnetic bubble memory is described. Key results include: (1) demonstration that self-structured bubbles (a lattice of strongly interacting bubbles) will slip by one another in a storage loop at spacings of 2.5 bubble diameters, (2) the ability of self-structured bubbles to move past international fabrication defects (missing apertures) in the propagation conductors (defeat tolerance), and (3) moving bubbles at mobility limited speeds. Milled barriers in the epitaxial garnet are discussed for containment of the bubble lattice. Experimental work on input/output tracks, storage loops, gates, generators, and magneto-resistive detectors for a prototype device are discussed. Potential final device architectures are described with modeling of power consumption, data rates, and access times. Appendices compare the self-structured bubble memory from the device and system perspectives with other non-volatile memory technologies

TANOS Charge-Trapping Flash Memory Structures

This work endeavored to optimize and integrate a process for depositing and patterning the gate film stack of TaN, Al 2O3, Si3N4, SiO2 , Si (TANOS) charge-trapping flash (CTF) memory with an existing complementary metal-oxidesemiconductor process flow. Fabricated capacitance-voltage devices with T-A-N-O thicknesses of 2500A° , 110A° , 75A° , and 30A° respectively show characteristic charge-trapping in subsequent program/erase (P/E) cycles (likely modified Fowler-Nordheim tunneling) with a maximum possible program threshold voltage of 2.7V for 5sec 28V program and minimum erased threshold voltage of -2.5V for 5sec 15V erase, w/ total P/E threshold voltage swing 5.2V. Device wafers are currently at step 22 of 67 and will be continued in the future, eventually demonstrating hot carrier injection P/E schemes Index Terms —Charge-Trap, EEPROM, Energy Band Engineering, Flash, Fowler-Nordheim Tunneling, Gate Stack, HEI, MANOS, Nitride, TANOS, Tantalu