Utilización del emulador em88110 para la realización de prácticas de las asignaturas del plan 96 de la Facultad de Informática de la U.P.M.

La introducción del nuevo plan de estudios de la Facultad de Informática de la U.P.M. con la correspondiente reestructuración de las asignaturas que cubren los conocimientos de Estructura y Arquitectura de Computadores. ha hecho necesaria la reestructuración del contenido práctico de dichas asignaturas, en la que se ha considerado la necesidad de incluir prácticas en las que se contemplen conceptos considerados básicos en la actualidad. Por otra parte. la realización de prácticas sobre una máquina real comercial (p.e. un SuperSparc) plantea una serie de inconvenientes que complican en exceso la asimilación de los conceptos que se desean comprender. Aquí se plantea la utilización de un emulador que proporcione al alumno un entorno de trabajo integrado. que pueda ejecutarse en distintas plataformas (desde PC's hasta estaciones de trabajo multiprocesador) y permita la realización de distintas prácticas. de complejidad progresiva. Con ello perseguimos afianzar los conocimientos teóricos que se deben adquirir, al cursar las asignaturas de Estructura, Laboratorio y Arquitectura de Computadores. las dos primeras correspondientes a segundo curso y la tercera a tercer curso

The Named-State Register File

This thesis introduces the Named-State Register File, a fine-grain, fully-associative register file. The NSF allows fast context switching between concurrent threads as well as efficient sequential program performance. The NSF holds more live data than conventional register files, and requires less spill and reload traffic to switch between contexts. This thesis demonstrates an implementation of the Named-State Register File and estimates the access time and chip area required for different organizations. Architectural simulations of large sequential and parallel applications show that the NSF can reduce execution time by 9% to 17% compared to alternative register files

A multiple-SIMD architecture for image and tracking analysis

The computational requirements for real-time image based applications are such as to warrant the use of a parallel architecture. Commonly used parallel architectures conform to the classifications of Single Instruction Multiple Data (SIMD), or Multiple Instruction Multiple Data (MIMD). Each class of architecture has its advantages and dis-advantages. For example, SIMD architectures can be used on data-parallel problems, such as the processing of an image. Whereas MIMD architectures are more flexible and better suited to general purpose computing. Both types of processing are typically required for the analysis of the contents of an image. This thesis describes a novel massively parallel heterogeneous architecture, implemented as the Warwick Pyramid Machine. Both SIMD and MIMD processor types are combined within this architecture. Furthermore, the SIMD array is partitioned, into smaller SIMD sub-arrays, forming a Multiple-SIMD array. Thus, local data parallel, global data parallel, and control parallel processing are supported. After describing the present options available in the design of massively parallel machines and the nature of the image analysis problem, the architecture of the Warwick Pyramid Machine is described in some detail. The performance of this architecture is then analysed, both in terms of peak available computational power and in terms of representative applications in image analysis and numerical computation. Two tracking applications are also analysed to show the performance of this architecture. In addition, they illustrate the possible partitioning of applications between the SIMD and MIMD processor arrays. Load-balancing techniques are then described which have the potential to increase the utilisation of the Warwick Pyramid Machine at run-time. These include mapping techniques for image regions across the Multiple-SIMD arrays, and for the compression of sparse data. It is envisaged that these techniques may be found useful in other parallel systems