Towards automated PCB routing: Leveraging machine learning and heuristic techniques

Printed Circuit Boards (PCBs) serve as the foundation of electronic products, facilitating the physical and electrical integration of electronic components. PCB routing, a crucial step of design, computationally determines optimal paths for metal traces based on component placement and connectivity requirements. However, with advancing integrated circuit technology, the complexity of routing increases, leading to time-consuming and error-prone processes. Current PCB routing paradigms often separate routing into escape and area routing stages, but this isolation can result in suboptimal solutions. In addition, existing routing algorithms are typically specialized and lack adaptability to address evolving design needs. Moreover, the absence of standardized benchmarks impedes the assessment of new routing approaches, particularly those incorporating machine learning techniques. To tackle these challenges, this dissertation proposes novel routing algorithms and a comprehensive dataset of real-world PCB designs. The research unfolds in three distinct parts. In the first part, we propose an end-to-end solution using Monte Carlo tree search (MCTS) and deep reinforcement learning (DRL). This approach employs a designed MCTS for circuit routing, guided by a deep reinforcement learning policy in the rollout. Notably, our method can be easily extended to routing cases with diverse routing constraints and optimization goals. Experimental results underscore the superiority of our approach, showcasing the highest success rates and minimized total wirelengths compared to traditional sequential A*-based routers on the test set. In the second part, we introduce a pad-focused, net-by-net, two-stage PCB routing methodology. This comprises an MCTS-based global routing stage followed by an A*-based detailed routing stage. To minimize the gap between the proposed global and detailed routing, a polygon-based dynamic routable region partitioning mechanism is introduced to guarantee the existence of a detailed routing solution when a global routing solution exists. Our experiments demonstrate the outperformance of our approach against both state-of-the-art academic and non-academic routers, evident in terms of enhanced routability and reduced wirelength. In the third part, we address the absence of standardized benchmarks in PCB routing by curating a dataset of community-endorsed, real-world, open-source PCB designs. This dataset, formatted in JSON, exclusively contains routing-related information represented through basic geometric objects and data structures. Notably, our dataset is 100 times larger than those used in recent PCB routing papers and is expandable through our versatile script supporting various input formats. Additionally, we provide a highly adaptable reinforcement learning (RL) environment tailored for the development and testing of RL-based PCB routing algorithms. We anticipate that this dataset will bridge the gap between the ML and PCB communities, fostering research into automated circuit design using machine learning, including generative PCB routing

Graphics Processing Unit-Based Computer-Aided Design Algorithms for Electronic Design Automation

The electronic design automation (EDA) tools are a specific set of software that play important roles in modern integrated circuit (IC) design. These software automate the design processes of IC with various stages. Among these stages, two important EDA design tools are the focus of this research: floorplanning and global routing. Specifically, the goal of this study is to parallelize these two tools such that their execution time can be significantly shortened on modern multi-core and graphics processing unit (GPU) architectures. The GPU hardware is a massively parallel architecture, enabling thousands of independent threads to execute concurrently. Although a small set of EDA tools can benefit from using GPU to accelerate their speed, most algorithms in this field are designed with the single-core paradigm in mind. The floorplanning and global routing algorithms are among the latter, and difficult to render any speedup on the GPU due to their inherent sequential nature. This work parallelizes the floorplanning and global routing algorithm through a novel approach and results in significant speedups for both tools implemented on the GPU hardware. Specifically, with a complete overhaul of solution space and design space exploration, a GPU-based floorplanning algorithm is able to render 4-166X speedup, while achieving similar or improved solutions compared with the sequential algorithm. The GPU-based global routing algorithm is shown to achieve significant speedup against existing state-of-the-art routers, while delivering competitive solution quality. Importantly, this parallel model for global routing renders a stable solution that is independent from the level of parallelism. In summary, this research has shown that through a design paradigm overhaul, sequential algorithms can also benefit from the massively parallel architecture. The findings of this study have a positive impact on the efficiency and design quality of modern EDA design flow

The IPS fidelity scale as a guideline to implement Supported Employment

info:eu-repo/semantics/publishe

Feasibility study for a numerical aerodynamic simulation facility. Volume 1

A Numerical Aerodynamic Simulation Facility (NASF) was designed for the simulation of fluid flow around three-dimensional bodies, both in wind tunnel environments and in free space. The application of numerical simulation to this field of endeavor promised to yield economies in aerodynamic and aircraft body designs. A model for a NASF/FMP (Flow Model Processor) ensemble using a possible approach to meeting NASF goals is presented. The computer hardware and software are presented, along with the entire design and performance analysis and evaluation

Researching methods for efficient hardware specification, design and implementation of a next generation communication architecture

The objective of this work is to create and implement a System Area Network (SAN) architecture called EXTOLL embedded in the current world of systems, software and standards based on the experiences obtained during the ATOLL project development and test. The topics of this work also cover system design methodology and educational issues in order to provide appropriate human resources and work premises. The scope of this work in the EXTOLL SAN project was: • the Xbar architecture and routing (multi-layer routing, virtual channels and their arbitration, routing formats, dead lock aviodance, debug features, automation of reuse) • the on-chip module communication architecture and parts of the host communication • the network processor architecture and integration • the development of the design methodology and the creation of the design flow • the team education and work structure. In order to successfully leverage student know-how and work flow methodology for this research project the SEED curricula changes has been governed by the Hochschul Didaktik Zentrum resulting in a certificate for "Hochschuldidaktik" and excellence in university education. The complexity of the target system required new approaches in concurrent Hardware/Software codesign. The concept of virtual hardware prototypes has been established and excessively used during design space exploration and software interface design

Journal of Telecommunications and Information Technology

kwartalni

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design