A forward body bias generator for digital CMOS circuits with supply voltage scaling

We propose a new fully-integrated forward body bias (FBB) generator that holds its voltage constant relative to the (scalable) power supply of a digital IP. The generator is modular and can drive distinct digital IP block sizes in multiples of up to 1mm2. The design has been implemented in 90nm low-power CMOS. Our basic unit for driving digital IP blocks up to 1mm2 occupies a silicon area of 0.03mm2 only. The generator completes a 500mV FBB voltage step within 4µs. The bandwidth of the design is 570kHz. The active current of the FBB generator alone is about 177µA for a nominal process, 1.2V supply and 85°C. The standby current is as low as 72nA at 27°C

Development of electrochromic thin-film transistors on flexible substrate

This work documents the fabrication and characterization of electrochromic thin-film transistors (ECTFTs) based on tungsten oxide (WO3). The ECTFTs exhibit double functionality (optical and electrical modulation) and were deposited on Corning glass and polyethylene naphthalate (PEN) by radio-frequency (RF) magnetron sputtering in an argon-oxygen atmospherewith no intentional substrate heating. The resulting amorphous WO3film connects source and drain in a planar configuration with three different architectures(conventional, interdigital and back-electrode) and isgated by a drop-casted lithium-based polymer electrolyte (LiClO4:PC). EC films were characterized using X-ray diffraction (XRD), atomic force microscopy (AFM)andopto-electrochemical measurements, the electrolyte by electrochemicalimpedance spectroscopy (EIS) and the ECTFTs by static and dynamic electrical characterization. Thinner EC films (75 nm) evidenced lower optical density (ΔOD) and color efficiency (CE) of 0,26 and 21,85 cm2C-1, respectively, but faster EC reaction kinetics, with bleaching and coloration times (tband tc) of 1,8 and 3,8 seconds, respectively. In terms of electrical properties the best performing ECTFT architecture (interdigital) showed an ION/IOFFof 2,81x105and a transconductance of 2,24 mS. The back-electrode architecturehowever showed better ionic movement control in the channel(adjustable VON)with enhanced colorations, making ita better candidate for a two-in-one (pixel + transistor) solution for display applications

Impact of atomistic device variability on analogue circuit design

Scaling of complementary metal-oxide-semiconductor (CMOS) technology has benefited the semiconductor industry for almost half a century. For CMOS devices with a physical gate-length in the sub-100 nm range, extreme device variability is introduced and has become a major stumbling block for next generation analogue circuit design. Both opportunities and challenges have therefore confronted analogue circuit designers. Small geometry device can enable high-speed analogue circuit designs, such as data conversion interfaces that can work in the radio frequency range. These designs can be co-integrated with digital systems to achieve low cost, high-performance, single-chip solutions that could only be achieved using multi-chip solutions in the past. However, analogue circuit designs are extremely vulnerable to device mismatch, since a large number of symmetric transistor pairs and circuit cells are required. The increase in device variability from sub-100 nm processes has therefore significantly reduced the production yield of the conventional designs. Mismatch models have been developed to analytically evaluate the magnitude of random variations. Based on measurements from custom designed test structures, the statistics of process variation can be estimated using design related parameters. However, existing models can no longer accurately estimate the magnitude of mismatch for sub-100 nm “atomistic” devices, since short-channel effects have become important. In this thesis, a new mismatch model for small geometry devices will be proposed to address this problem. Based on knowledge of the matching performance obtained from the mismatch model, design solutions are desired at different design levels for a variety of circuit topologies. In this thesis, transistor level compensation solutions have been investigated and closed-loop compensation circuits have been proposed. At circuit level, a latch-based comparator has been used to develop a compensation solution because this type of comparator is extremely sensitive to the device mismatch. These comparators are also used as the fundamental building block for the analogue-to-digital converters (ADC). The proposed comparator compensation scheme is used to improve the performance of a high-speed flash ADC