Analysis and design of power delivery networks exploiting simulation tools and numerical optimization techniques

A higher performance of computing systems is being demanded year after year, driving the digital industry to fiercely compete for offering the fastest computer system at the lowest cost. In addition, as computing system performance is growing, power delivery networks (PDN) and power integrity (PI) designs are getting increasingly more relevance due to the faster speeds and more parallelism required to obtain the required performance growth. The largest data throughput at the lowest power consumption is a common goal for most of the commercial computing systems. As a consequence of this performance growth and power delivery tradeoffs, the complexity involved in analyzing and designing PDN in digital systems is being increased. This complexity drives longer design cycle times when using traditional design tools. For this reason, the need of using more efficient design methods is getting more relevance in order to keep designing and launching products in a faster manner to the market. This trend pushes PDN designers to look for methodologies to simplify analysis and reduce design cycle times. The main objective for this Master’s thesis is to propose alternative methods by exploiting reliable simulation approaches and efficient numerical optimization techniques to analyze and design PDN to ensure power integrity. This thesis explores the use of circuital models and electromagnetic (EM) field solvers in combination with numerical optimization methods, including parameter extraction (PE) formulations. It also establishes a sound basis for using space mapping (SM) methodologies in future developments, in a way that we exploit the advantages of the most accurate and powerful models, such as 3D full-wave EM simulators, but conserving the simplicity and low computational resourcing of the analytical, circuital, and empirical models

Power distribution design for high-density packages

This thesis describes the design of a high-density power distribution system. Properties of impedances of power distribution systems are examined. Impedances are classified as self and trans-impedances. These properties are then used to save simulation time, which is a big factor for power distribution system design. Time domain models are extracted for the test cases. A novel 2D-3D technique of placing decoupling capacitors is demonstrated that is based on the effectiveness of the capacitor at that location. The power distribution system acts as a cavity resonator supporting discrete modes that vary with distance. Each capacitor is placed at the physical location where it has maximum impact on corresponding system modes. Targeting the modes at the ports where they are dominant using decoupling capacitors reduces trans-impedances. This technique is extended to the entire surface of the power distribution system using just a single set of simulations. This thesis presents a novel 2D-3D approach of designing high-density boards having chips with multiple power connections without having to go through lengthy tedious simulations

Scalable Analysis, Verification and Design of IC Power Delivery

Due to recent aggressive process scaling into the nanometer regime, power delivery network design faces many challenges that set more stringent and specific requirements to the EDA tools. For example, from the perspective of analysis, simulation efficiency for large grids must be improved and the entire network with off-chip models and nonlinear devices should be able to be analyzed. Gated power delivery networks have multiple on/off operating conditions that need to be fully verified against the design requirements. Good power delivery network designs not only have to save the wiring resources for signal routing, but also need to have the optimal parameters assigned to various system components such as decaps, voltage regulators and converters. This dissertation presents new methodologies to address these challenging problems. At first, a novel parallel partitioning-based approach which provides a flexible network partitioning scheme using locality is proposed for power grid static analysis. In addition, a fast CPU-GPU combined analysis engine that adopts a boundary-relaxation method to encompass several simulation strategies is developed to simulate power delivery networks with off-chip models and active circuits. These two proposed analysis approaches can achieve scalable simulation runtime. Then, for gated power delivery networks, the challenge brought by the large verification space is addressed by developing a strategy that efficiently identifies a number of candidates for the worst-case operating condition. The computation complexity is reduced from O(2^N) to O(N). At last, motivated by a proposed two-level hierarchical optimization, this dissertation presents a novel locality-driven partitioning scheme to facilitate divide-and-conquer-based scalable wire sizing for large power delivery networks. Simultaneous sizing of multiple partitions is allowed which leads to substantial runtime improvement. Moreover, the electric interactions between active regulators/converters and passive networks and their influences on key system design specifications are analyzed comprehensively. With the derived design insights, the system-level co-design of a complete power delivery network is facilitated by an automatic optimization flow. Results show significant performance enhancement brought by the co-design

Fast methods for full-wave electromagnetic simulations of integrated circuit package modules

Fast methods for the electromagnetic simulation of integrated circuit (IC) package modules through model order reduction are demonstrated. The 3D integration of multiple functional IC chip/package modules on a single platform gives rise to geometrically complex structures with strong electromagnetic phenomena. This motivates our work on a fast full-wave solution for the analysis of such modules, thus contributing to the reduction in design cycle time without loss of accuracy. Traditionally, fast design approaches consider only approximate electromagnetic effects, giving rise to lumped-circuit models, and therefore may fail to accurately capture the signal integrity, power integrity, and electromagnetic interference effects. As part of this research, a second order frequency domain full-wave susceptance element equivalent circuit (SEEC) model will be extracted from a given structural layout. The model so obtained is suitably reduced using model order reduction techniques. As part of this effort, algorithms are developed to produce stable and passive reduced models of the original system, enabling fast frequency sweep analysis. Two distinct projection-based second order model reduction approaches will be considered: 1) matching moments, and 2) matching Laguerre coefficients, of the original system's transfer function. Further, the selection of multiple frequency shifts in these schemes to produce a globally representative model is also studied. Use of a second level preconditioned Krylov subspace process allows for a memory-efficient way to address large size problems.Ph.D.Committee Chair: Swaminathan Madhavan; Committee Member: Papapolymerou John; Committee Member: Chatterjee Abhijit; Committee Member: Peterson Andrew; Committee Member: Sitaraman Sures

Physical parameter-aware Networks-on-Chip design

PhD ThesisNetworks-on-Chip (NoCs) have been proposed as a scalable, reliable and power-efficient communication fabric for chip multiprocessors (CMPs) and multiprocessor systems-on-chip (MPSoCs). NoCs determine both the performance and the reliability of such systems, with a significant power demand that is expected to increase due to developments in both technology and architecture. In terms of architecture, an important trend in many-core systems architecture is to increase the number of cores on a chip while reducing their individual complexity. This trend increases communication power relative to computation power. Moreover, technology-wise, power-hungry wires are dominating logic as power consumers as technology scales down. For these reasons, the design of future very large scale integration (VLSI) systems is moving from being computation-centric to communication-centric. On the other hand, chip’s physical parameters integrity, especially power and thermal integrity, is crucial for reliable VLSI systems. However, guaranteeing this integrity is becoming increasingly difficult with the higher scale of integration due to increased power density and operating frequencies that result in continuously increasing temperature and voltage drops in the chip. This is a challenge that may prevent further shrinking of devices. Thus, tackling the challenge of power and thermal integrity of future many-core systems at only one level of abstraction, the chip and package design for example, is no longer sufficient to ensure the integrity of physical parameters. New designtime and run-time strategies may need to work together at different levels of abstraction, such as package, application, network, to provide the required physical parameter integrity for these large systems. This necessitates strategies that work at the level of the on-chip network with its rising power budget. This thesis proposes models, techniques and architectures to improve power and thermal integrity of Network-on-Chip (NoC)-based many-core systems. The thesis is composed of two major parts: i) minimization and modelling of power supply variations to improve power integrity; and ii) dynamic thermal adaptation to improve thermal integrity. This thesis makes four major contributions. The first is a computational model of on-chip power supply variations in NoCs. The proposed model embeds a power delivery model, an NoC activity simulator and a power model. The model is verified with SPICE simulation and employed to analyse power supply variations in synthetic and real NoC workloads. Novel observations regarding power supply noise correlation with different traffic patterns and routing algorithms are found. The second is a new application mapping strategy aiming vii to minimize power supply noise in NoCs. This is achieved by defining a new metric, switching activity density, and employing a force-based objective function that results in minimizing switching density. Significant reductions in power supply noise (PSN) are achieved with a low energy penalty. This reduction in PSN also results in a better link timing accuracy. The third contribution is a new dynamic thermal-adaptive routing strategy to effectively diffuse heat from the NoC-based threedimensional (3D) CMPs, using a dynamic programming (DP)-based distributed control architecture. Moreover, a new approach for efficient extension of two-dimensional (2D) partially-adaptive routing algorithms to 3D is presented. This approach improves three-dimensional networkon- chip (3D NoC) routing adaptivity while ensuring deadlock-freeness. Finally, the proposed thermal-adaptive routing is implemented in field-programmable gate array (FPGA), and implementation challenges, for both thermal sensing and the dynamic control architecture are addressed. The proposed routing implementation is evaluated in terms of both functionality and performance. The methodologies and architectures proposed in this thesis open a new direction for improving the power and thermal integrity of future NoC-based 2D and 3D many-core architectures

The Development of Novel Interconnection Technologies for 3D Packaging of Wire Bondless Silicon Carbide Power Modules

This dissertation advances the cause for the 3D packaging and integration of silicon carbide power modules. 3D wire bondless approaches adopted for enhancing the performance of silicon power modules were surveyed, and their merits were assessed to serve as a vision for the future of SiC power packaging. Current efforts pursuing 3D wire bondless SiC power modules were investigated, and the concept for a novel SiC power module was discussed. This highly-integrated SiC power module was assessed for feasibility, with a focus on achieving ultralow parasitic inductances in the critical switching loops. This will enable higher switching frequencies, leading to a reduction in the size of the passive devices in the system and resulting in systems with lower weight and volume. The proposed concept yielded an order-of-magnitude reduction in system parasitics, alongside the possibility of a compact system integration. The technological barriers to realizing these concepts were identified, and solutions for novel interconnection schemes were proposed and evaluated. A novel sintered silver preform was developed to facilitate flip-chip interconnections for a bare-die power device while operating in a high ambient temperature. The preform was demonstrated to have 3.75× more bonding strength than a conventional sintered silver bond and passed rigorous thermal shock tests. A chip-scale and flip-chip capable power device was also developed. The novel package combined the ease of assembly of a discrete device with a performance exceeding a wire bonded module. It occupied a 14× smaller footprint than a discrete device, and offered power loop inductances which were less than a third of a conventional wire bonded module. A detailed manufacturing process flow and qualification is included in this dissertation. These novel devices were implemented in various electrical systems—a discrete Schottky barrier diode package, a half-bridge module with external gate drive, and finally a half-bridge with integrated gate driver in-module. The results of these investigations have been reported and their benefits assessed. The wire bondless modules showed \u3c 5% overshoot under all test conditions. No observable detrimental effects due to dv/dt were observed for any of the modules even under aggressive voltage slew rates of 20-25 V/ns

Clock Polarity Assignment Methodologies for Designing High-Performance and Robust Clock Trees

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2016. 8. 김태환.In modern synchronous circuits, the system relies on one single signal, namely, the clock signal. All data sampling of flip-flops rely on the timing of the clock signal. This makes clock trees, which deliver the clock signal to every clock sink in the whole system, one of the most active components on a chip, as it must switch without halting. Naturally, this makes clock trees a primary target of optimization for low power/high performance designs. First, bounded skew clock polarity assignment is explored. Buffers in the clock tree switch simultaneously as the clock signal switch, which causes power/ground supply voltage fluctuation. This phenomenon is referred to as clock noise and brings adverse effects on circuit robustness. Clock polarity assignment technique replaces some of the buffers in the clock trees with inverters. Since buffers draw larger current at the rising edge of the clock while inverters draw larger current at the falling edge, this technique can mitigate peak noise problem at the power/ground supply rails. Second, useful skew clock polarity assignment method is developed. Useful clock skew methodology allows consideration of individual clock skew restraints between each clock sinks, allowing further noise reduction by exploiting more time slack. Through experiments with ISPD 2010 clock network synthesis contest benchmark circuits, the results show that the proposed clock polarity algorithm is able to reduce the peak noise caused by clock buffers by 10.9% further over that of the global skew bound constrained polarity assignment while satisfying all setup and hold time constraints. Lastly, as multi-corner multi-mode (MCMM) design methodologies, process variations and clock gating techniques are becoming common place in advanced technology nodes, clock polarity assignment methods that mitigate these problems are devised. Experimental results indicate that the proposed methods successfully satisfy required design constraints imposed by such variations. In summary, this dissertation presents clock polarity assignments that considers useful clock skew, delay variations, MCMM design methodologies and clock gating techniques.Chapter 1 Introduction 1 1.1 Clock Trees 1 1.2 Simultaneous Switching Noise 3 1.3 Clock Polarity Assignment Technique 4 1.4 Contributions of this Dissertation 5 Chapter 2 Clock Polarity Assignment Under Bounded Skew 7 2.1 Introduction 7 2.2 Motivational Example 9 2.3 Problem Formulation 13 2.4 Proposed Algorithm 17 2.4.1 Independence Assumption 17 2.4.2 Characterization of Noise 18 2.4.3 Overview of the Proposed Algorithm 19 2.4.4 Mapping WaveMin Problem to MOSP problem 22 2.4.5 A Fast Algorithm 26 2.4.6 Zone Sizing/Partitioning Method 27 2.5 Experimental Results 28 2.5.1 Experimental Setup 28 2.5.2 Noise Reduction 28 2.5.3 Simulation on Full Circuit 29 2.6 Effects of Clock Polarity Assignment on Simultaneous Switching Noise 34 2.6.1 Model of Power Delivery Network 34 2.6.2 Peak-to-Peak Voltage Swing 35 2.7 Effects of Decoupling Capacitors 36 2.8 Effects of Clock Polarity Assignment on Clock Jitter 40 2.8.1 Noise in Frequency Domain 40 2.9 Summary 43 Chapter 3 Clock Polarity Assignment Under Useful Skew 44 3.1 Introduction 44 3.2 Motivational Example 45 3.3 Problem Formulation 47 3.4 Proposed Algorithm 49 3.4.1 Integer Linear Programming Formulation and Linear Programming Relaxation 49 3.4.2 Formulating into Maximum Clique Problem 49 3.4.3 Scalable Algorithm for Clique Exploration 51 3.5 Experimental Results 54 3.5.1 Experimental Setup 54 3.5.2 Assessing the Performance of UsefulMin over Wavemin 56 3.6 Summary 57 Chapter 4 Extensions of Clock Polarity Assignment Methods 60 4.1 Coping With Thermal Variations 60 4.1.1 Introduction 60 4.1.2 Proposed Method 61 4.1.3 Experimental Results 66 4.2 Coping with Delay Variations 70 4.2.1 Introduction 70 4.2.2 The Impact of Process Variations on Polarity Assignment 71 4.2.3 Proposed Method for Variation Resiliency 72 4.2.4 Experimental Results 73 4.3 Coping With Multi-Mode Designs 75 4.3.1 Introduction 75 4.3.2 Proposed Method 76 4.3.3 Experimental Results 84 4.4 Orthogonality with Other Design Techniques ? Clock Gating 87 4.4.1 Introduction 87 4.4.2 Proposed Partitioning Method 87 4.4.3 Experimental Results 88 4.5 Summary 90 Chapter 5 Conclusion 92 5.1 Clock Polarity Assignment Under Bounded Skew 92 5.2 Clock Polarity Assignment Under Useful Skew 93 5.3 Extensions of Clock Polarity Assignment 93 Appendices 94 Chapter A Power Spectral Densities of ISCAS89 Circuits 95 Chapter B The Effect of Decoupling Capacitors 99 초록 109Docto

Printed circuit board power distribution network modeling, analysis and design, and, statistical crosstalk analysis for high speed digital links

High-speed digital systems are moving to higher data rates and smaller supply voltages as the scale of integration goes smaller. With the smaller bit periods and the smaller operating voltages, the tolerable timing and noise margins are reducing. There are many sources of disturbances contributing to the tolerance margins. These margins have to account for inter symbol interference (ISI), reflections, jitter, noise from power distribution networks (PDN) and crosstalk. An important task during the design phase of the system is to find and mitigate the noise from such sources. This thesis proposes modeling and analysis methodology to resolve some of the problems while proposing relevant design methodologies to reduce the system design cycles. PDN design forms a critical part of a high-speed digital design to provide a low-noise power supply to the integrated circuits (ICs) within some peak voltage ripple for normal functioning. Switching of transistors in the IC leads to a high-frequency current draw and generates the simultaneous switching noise (SSN), which propagates along the PDN from the chip to the PCB and causes several EMI and SI problems. A physics-based modeling approach for PCB PDN is proposed which is used for analysis and design guideline development. A design methodology is developed which guides the designer to make better design decisions, knowing the impact on PDN performance without the use of full-wave tools. Crosstalk forms a critical part of the budget, and if ignored, can lead to design failures. A statistical method to find the distribution of crosstalk at the victim using the single bit response principle is proposed. The methodology is extended to multiple-aggressor system, and, can be used to identify worst case crosstalk and find dominant crosstalk contributors in a system. --Abstract, page iii

Multiphysics modeling and simulation for large-scale integrated circuits

This dissertation is a process of seeking solutions to two important and challenging problems related to the design of modern integrated circuits (ICs): the ever increasing couplings among the multiphysics and the large problem size arising from the escalating complexity of the designs. A multiphysics-based computer-aided design methodology is proposed and realized to address multiple aspects of a design simultaneously, which include electromagnetics, heat transfer, fluid dynamics, and structure mechanics. The multiphysics simulation is based on the finite element method for its unmatched capabilities in handling complicate geometries and material properties. The capability of the multiphysics simulation is demonstrated through its applications in a variety of important problems, including the static and dynamic IR-drop analyses of power distribution networks, the thermal-ware high-frequency characterization of through-silicon-via structures, the full-wave electromagnetic analysis of high-power RF/microwave circuits, the modeling and analysis of three-dimensional ICs with integrated microchannel cooling, the characterization of micro- and nanoscale electrical-mechanical systems, and the modeling of decoupling capacitor derating in the power integrity simulations. To perform the large-scale analysis in a highly efficient manner, a domain decomposition scheme, parallel computing, and an adaptive time-stepping scheme are incorporated into the proposed multiphysics simulation. Significant reduction in computation time is achieved through the two numerical schemes and the parallel computing with multiple processors