Efficient Support for Video Communications in Wireless Home Networks

This paper investigates the performance of video communications over wireless networks employing the recently proposed Time-Division Unbalanced Carrier Sense Multiple access (TDuCSMA) coordination function. TDuCSMA is fully IEEE 802.11 standard compliant but offers novel bandwidth management capabilities. In this work the peculiar characteristics of TDuCSMA are configured and exploited to maximize the performance of video communications in a realistic home networking scenario. Simulation results show significant performance improvements with respect to legacy IEEE 802.11 network. The video quality gains are up to 13 dB PSNR with 500 ms playout buffer, while the average delay of the video packets is much lower, for the same amount of video traffic offered to the network. These results significantly contribute to enhance the quality of experience of the users of the video communicatio

Network Coding Enabled Named Data Networking Architectures

The volume of data traffic in the Internet has increased drastically in the last years, mostly due to data intensive applications like video streaming, file sharing, etc.. This motivates the development of new communication methods that can deal with the growing volume of data traffic. To this aim, Named Data Networking (NDN) has been proposed as a future Internet architecture that changes how the Internet works, from the exchange of content between particular nodes of the network, to retrieval of particular content in the network. The NDN architecture enables ubiquitous in-network caching and naturally supports dynamic selection of content sources, characteristics that fit well with the communication needs of data intensive applications. However, the performance of data intensive applications is degraded by the limited throughput seen by applications, which can be caused by (i) limited bandwidth, (ii) network bottlenecks and (iii) packet losses. In this thesis, we argue that introducing network coding into the NDN architecture improves the performance of NDN-based data intensive applications by alleviating the three issues presented above. In particular, network coding (i) enables efficient multipath data retrieval in NDN, which allows nodes to aggregate all the bandwidth available through their multiple interfaces; (ii) allows information from multiple sources to be combined at the intermediate routers, which alleviates the impact of network bottlenecks; and (iii) enables clients to efficiently handle packet losses. This thesis first provides an architecture that enables network coding in NDN for data intensive applications. Then, a study demonstrates and quantifies the benefits that network coding brings to video streaming over NDN, a particular data intensive application. To study the benefits that network coding brings in a more realistic NDN scenario, this thesis finally provides a caching strategy that is used when the in-network caches have limited capacity. Overall, the evaluation results show that the use of network coding permits to exploit more efficiently available network resources, which leads to reduced data traffic load on the sources, increased cache-hit rate at the in-network caches and faster content retrieval at the clients. In particular, for video streaming applications, network coding enables clients to watch higher quality videos compared to using traditional NDN, while it also reduces the video servers' load. Moreover, the proposed caching strategy for network coding enabled NDN maintains the benefits that network coding brings to NDN even when the caches have limited storage space

Scalable reconfigurable computing leveraging latency-insensitive channels

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 190-197).Traditionally, FPGAs have been confined to the limited role of small, low-volume ASIC replacements and as circuit emulators. However, continued Moore's law scaling has given FPGAs new life as accelerators for applications that map well to fine-grained parallel substrates. Examples of such applications include processor modelling, compression, and digital signal processing. Although FPGAs continue to increase in size, some interesting designs still fail to fit in to a single FPGA. Many tools exist that partition RTL descriptions across FPGAs. Unfortunately, existing tools have low performance due to the inefficiency of maintaining the cycle-by-cycle behavior of RTL among discrete FPGAs. These tools are unsuitable for use in FPGA program acceleration, as the purpose of an accelerator is to make applications run faster. This thesis presents latency-insensitive channels, a language-level mechanism by which programmers express points in their their design at which the cycle-by-cycle behavior of the design may be modified by the compiler. By decoupling the timing of portions of the RTL from the high-level function of the program, designs may be mapped to multiple FPGAs without suffering the performance degradation observed in existing tools. This thesis demonstrates, using a diverse set of large designs, that FPGA programs described in terms of latency-insensitive channels obtain significant gains in design feasibility, compilation time, and run-time when mapped to multiple FPGAs.by Kermin Elliott Fleming, Jr.Ph.D

A Scalable and Adaptive Network on Chip for Many-Core Architectures

In this work, a scalable network on chip (NoC) for future many-core architectures is proposed and investigated. It supports different QoS mechanisms to ensure predictable communication. Self-optimization is introduced to adapt the energy footprint and the performance of the network to the communication requirements. A fault tolerance concept allows to deal with permanent errors. Moreover, a template-based automated evaluation and design methodology and a synthesis flow for NoCs is introduced