08201 Abstracts Collection -- Design and Analysis of Randomized and Approximation Algorithms

From 11.05.08 to 16.05.08, the Dagstuhl Seminar 08201 ``Design and Analysis of Randomized and Approximation Algorithms\u27\u27 was held in the International Conference and Research Center (IBFI), Schloss Dagstuhl. During the seminar, several participants presented their current research work, and ongoing work and open problems were discussed. Abstracts of the presentations which were given during the seminar as well as abstracts of seminar results and ideas are put together in this paper. The first section describes the seminar topics and goals in general. Links to extended abstracts or full paper are provided, if available

Improved Physical Design for Manufacturing Awareness and Advanced VLSI

Increasing challenges arise with each new semiconductor technology node, especially in advanced nodes, where the industry tries to extract every ounce of benefit as it approaches the limits of physics, through manufacturing-aware design technology co-optimization and design-based equivalent scaling. The increasing complexity of design and process technologies, and ever-more complex design rules, also become hurdles for academic researchers, separating academic researchers from the most up-to-date technical issues.This thesis presents innovative methodologies and optimizations to address the above challenges. There are three directions in this thesis: (i) manufacturing-aware design technology co-optimization; (ii) advanced node design-based equivalent scaling; and (iii) an open source academic detailed routing flow.To realize manufacturing-aware design technology co-optimization, this thesis presents two works: (i) a multi-row detailed placement optimization for neighbor diffusion effect mitigation between neighboring standard cells; and (ii) a post-routing optimization to generate 2D block mask layout for dummy segment removal in self-aligned multiple patterning.To achieve advanced node design-based equivalent scaling, this thesis presents two improved physical design methodologies: (i) a post-placement flop tray generation approach for clock power reduction; and (ii) a detailed placement approach to exploit inter-row M1 routing for congestion and wirelength reduction.To address the increasing gap between academia and industry, this thesis presents two works toward an open source academic detailed routing flow: (i) a complete, robust, scalable and design ruleaware dynamic programming-based pin access analysis framework; and (ii) TritonRoute – the open source detailed router that is capable of delivering DRC-clean detailed routing solutions in advanced nodes.This thesis concludes with a summary of its contributions and open directions for future research

Computational predictions of energy materials using density functional theory

In the search for new functional materials, quantum mechanics is an exciting starting point. The fundamental laws that govern the behaviour of electrons have the possibility, at the other end of the scale, to predict the performance of a material for a targeted application. In some cases, this is achievable using density functional theory (DFT). In this Review, we highlight DFT studies predicting energy-related materials that were subsequently confirmed experimentally. The attributes and limitations of DFT for the computational design of materials for lithium-ion batteries, hydrogen production and storage materials, superconductors, photovoltaics and thermoelectric materials are discussed. In the future, we expect that the accuracy of DFT-based methods will continue to improve and that growth in computing power will enable millions of materials to be virtually screened for specific applications. Thus, these examples represent a first glimpse of what may become a routine and integral step in materials discovery

Properties and Manipulation of Ionic Liquid-Solid Interfaces in Complex Oxide Materials

Ionic liquids are liquid salts that are bringing rapid changes to the field of solid electronic materials. The implementation of ionic liquids in conjunction with these solid materials produces interfacial effects, especially when a bias is applied across the ionic liquid, forming an electric double layer. Electric double layers in ionic liquids are unique in their formation and the interfacial charges that are orders of magnitude higher than conventional techniques they can impart, providing new techniques for device design and implementation. In chapter 1, the fundamentals of the solid state electronic and magnetic materials are introduced, along with ionic liquids, and their essential properties that make them appropriate for use with solid films. Chapter 2 discusses the geometric impacts that should be taken into consideration when designing electric double layer devices, determining that the gate area to device area ratio plays the greatest role. Chapter 3 explores the application of electric double layer interfacial effects on ferroelectric lead zirconate- titanate films. The demonstrated large area switching, coupled with the minimal changes to film quality, and use on low quality films make this ionic liquid-solid interface an exciting proposition for future study and applications. Chapter 4 uses the same electric double layer to interrogate the ability to produce stoichiometry induced crystallographic transformations in strontium cobaltite family of films. Chapter 5 evaluates an antiferromagnetic lanthanum-strontium manganite that shows an unprecedented anisotropic magnetoresistance. These materials are excellent candidates for future spin based devices. The work discussed in this dissertation demonstrates a wide range of possible applications that can be affected by the use of ionic liquid solid interfaces, while also showing diversity in the types of studies and measurements that can be conducted by ionic liquids. Combining the electrostatic and electrochemical capabilities of ionic liquids with complex oxide films, the manipulation oxide properties can lead to advances in future electronic and magnetic properties and applications

Quantum Transport Simulation of III-V TFETs with Reduced-Order K.P Method

III-V tunneling field-effect transistors (TFETs) offer great potentials in future low-power electronics application due to their steep subthreshold slope and large "on" current. Their 3D quantum transport study using non-equilibrium Green's function method is computationally very intensive, in particular when combined with multiband approaches such as the eight-band K.P method. To reduce the numerical cost, an efficient reduced-order method is developed in this article and applied to study homojunction InAs and heterojunction GaSb-InAs nanowire TFETs. Device performances are obtained for various channel widths, channel lengths, crystal orientations, doping densities, source pocket lengths, and strain conditions

Transparent and ‘opaque’ conducting electrodes for ultra-thin highly-efficient near-field thermophotovoltaic cells

Transparent conducting electrodes play a fundamental role in far-field PhotoVoltaic systems, but have never been thoroughly investigated for near-field applications. Here we show, in the context of near-field planar ultra-thin ThermoPhotoVoltaic cells using surface-plasmon-polariton thermal emitters, that the resonant nature of the nanophotonic system significantly alters the design criteria for the necessary conducting front electrode. The traditional ratio of optical-to-DC conductivities is alone not an adequate figure of merit, instead the desired impedance matching between the emitter and absorber modes along with their coupling to the free-carrier resonance of the front electrode are key for optimal device design and performance. Moreover, we demonstrate that conducting electrodes 'opaque' to incoming far-field radiation can, in fact, be used in the near field with decent performance by taking advantage of evanescent photon tunneling from the emitter to the absorber. Finally, we identify and compare appropriate tunable-by-doping materials for front electrodes in near-field ThermoPhotoVoltaics, specifically molybdenum-doped indium oxide, dysprosium-doped cadmium oxide, graphene and diffused semiconductors, but also for 'opaque' electrodes, tin-doped indium oxide and silver nano-films. Predicted estimated performances include output power density ~10 W/cm 2 with > 45% efficiency at 2100 °K emitter temperature and 60 Ω electrode square resistance, thus increasing the promise for high-performance practical devices.Massachusetts Institute of Technology. Institute for Soldier Nanotechnologies ( Contract W911NF-13-D-0001

EFFICIENT HARDWARE PRIMITIVES FOR SECURING LIGHTWEIGHT SYSTEMS

In the era of IoT and ubiquitous computing, the collection and communication of sensitive data is increasingly being handled by lightweight Integrated Circuits. Efficient hardware implementations of crytographic primitives for resource constrained applications have become critical, especially block ciphers which perform fundamental operations such as encryption, decryption, and even hashing. We study the efficiency of block ciphers under different implementation styles. For low latency applications that use unrolled block cipher implementations, we design a glitch filter to reduce energy consumption. For lightweight applications, we design a novel architecture for the widely used AES cipher. The design eliminates inefficiencies in data movement and clock activity, thereby significantly improving energy efficiency over state-of-the-art architectures. Apart from efficiency, vulnerability to implementation attacks are a concern, which we mitigate by our randomization capable lightweight AES architecture. We fabricate our designs in a commercial 16nm FinFET technology and present measured testchip data on energy consumption and side channel resistance. Finally, we address the problem of supply chain security by using image processing techniques to extract fingerprints from surface texture of plastic IC packages for IC authentication and counterfeit prevention. Collectively these works present efficient and cost effective solutions to secure lightweight systems

Design Methodologies and Architecture Solutions for High-Performance Interconnects

ABSTRACT In Deep Sub-Micron (DSM) technologies, interconnects play a crucial role in the correct functionality and largely impact the performance of complex System-on-Chip (SoC) designs. For technologies of 0.25µm and below, wiring capacitance dominates gate capacitance, thus rapidly increasing the interconnect-induced delay. Moreover, the coupling capacitance becomes a significant portion of the on-chip total wiring capacitance, and coupling between adjacent wires cannot be considered as a second-order effect any longer. As a consequence, the traditional top-down design methodology is ineffective, since the actual wiring delays can be computed only after layout parasitic extraction, when the physical design is completed. Fixing all the timing violations often requires several time-consuming iterations of logical and physical design, and it is essentially a trial-and-error approach. Increasingly tighter time-to-market requirements dictate that interconnect parasitics must be taken into account during all phases of the design flow, at different level of abstractions. However, given the aggressive technology scaling trends and the growing design complexity, this approach will only temporarily ameliorate the interconnect problem. We believe that in order to achieve gigascale designs in the nanometer regime, a novel design paradigm, based on new forms of regularity and newly created IP (Intellectual Property) blocks must be developed, to provide a direct path from system-level architectural exploration to physical implementation