NAND Flash Memory Characterization

The NAND technology has become a popular research area and implementation choice due to its non-volatile flash memory characteristics. There are many engineering challenges when it comes to NAND technology. Some of the limiting factors are reducing the transistor width and increasing read and write performance. The device physics for NAND floating gate cell technology also introduces challenges. Using a floating gate transistor that can address up to 4 bits per cell allows for higher density. However, this introduces a higher internal current leakage that can cause read and program inaccuracies. With floating-gate 3D NAND technology, we are able to better the data retention and have better QLC (Quad-Level Cell) capability. 3D NAND technology has a series of memory cells interconnected that can achieve higher data density and increased storage capacity. In this research, the Gen-4 NAND Flash device functionality is explored by design validation to achieve higher solid-state drive performance. This technology is 144-Layer QLC NAND Flash which is 1024Gb in density. My contributions are implemented showing improved read and write performance for customer operations and how inaccuracies are dealt with from a software and hardware perspective. Silicon wafer testing is also explored to fully characterize and analyze the problem

High-Density Solid-State Memory Devices and Technologies

This Special Issue aims to examine high-density solid-state memory devices and technologies from various standpoints in an attempt to foster their continuous success in the future. Considering that broadening of the range of applications will likely offer different types of solid-state memories their chance in the spotlight, the Special Issue is not focused on a specific storage solution but rather embraces all the most relevant solid-state memory devices and technologies currently on stage. Even the subjects dealt with in this Special Issue are widespread, ranging from process and design issues/innovations to the experimental and theoretical analysis of the operation and from the performance and reliability of memory devices and arrays to the exploitation of solid-state memories to pursue new computing paradigms

Flash Memory Devices

Flash memory devices have represented a breakthrough in storage since their inception in the mid-1980s, and innovation is still ongoing. The peculiarity of such technology is an inherent flexibility in terms of performance and integration density according to the architecture devised for integration. The NOR Flash technology is still the workhorse of many code storage applications in the embedded world, ranging from microcontrollers for automotive environment to IoT smart devices. Their usage is also forecasted to be fundamental in emerging AI edge scenario. On the contrary, when massive data storage is required, NAND Flash memories are necessary to have in a system. You can find NAND Flash in USB sticks, cards, but most of all in Solid-State Drives (SSDs). Since SSDs are extremely demanding in terms of storage capacity, they fueled a new wave of innovation, namely the 3D architecture. Today “3D” means that multiple layers of memory cells are manufactured within the same piece of silicon, easily reaching a terabit capacity. So far, Flash architectures have always been based on "floating gate," where the information is stored by injecting electrons in a piece of polysilicon surrounded by oxide. On the contrary, emerging concepts are based on "charge trap" cells. In summary, flash memory devices represent the largest landscape of storage devices, and we expect more advancements in the coming years. This will require a lot of innovation in process technology, materials, circuit design, flash management algorithms, Error Correction Code and, finally, system co-design for new applications such as AI and security enforcement