Developing Analytical and Communication Skills in a Mock-Trial Course Based on the Famous Woburn, Massachusetts Case

This Journal of Geoscience Education article discusses a mock trial in which undergraduates serve as expert witnesses and law students serve as their attorneys. The article identifies the trial as an effective vehicle for developing quantitative skills and enhancing written and oral communication skills. The course discussed is unabashedly about applying scientific principles to solve real-world problems. The entire course revolves around the analysis, interpretation, and presentation of scientific data. Educational levels: Graduate or professional, Undergraduate lower division, Undergraduate upper division

Defragmenting the Module Layout of a Partially Reconfigurable Device

Modern generations of field-programmable gate arrays (FPGAs) allow for partial reconfiguration. In an online context, where the sequence of modules to be loaded on the FPGA is unknown beforehand, repeated insertion and deletion of modules leads to progressive fragmentation of the available space, making defragmentation an important issue. We address this problem by propose an online and an offline component for the defragmentation of the available space. We consider defragmenting the module layout on a reconfigurable device. This corresponds to solving a two-dimensional strip packing problem. Problems of this type are NP-hard in the strong sense, and previous algorithmic results are rather limited. Based on a graph-theoretic characterization of feasible packings, we develop a method that can solve two-dimensional defragmentation instances of practical size to optimality. Our approach is validated for a set of benchmark instances.Comment: 10 pages, 11 figures, 1 table, Latex, to appear in "Engineering of Reconfigurable Systems and Algorithms" as a "Distinguished Paper

Taming a non-convex landscape with dynamical long-range order: memcomputing Ising benchmarks

Recent work on quantum annealing has emphasized the role of collective behavior in solving optimization problems. By enabling transitions of clusters of variables, such solvers are able to navigate their state space and locate solutions more efficiently despite having only local connections between elements. However, collective behavior is not exclusive to quantum annealers, and classical solvers that display collective dynamics should also possess an advantage in navigating a non-convex landscape. Here, we give evidence that a benchmark derived from quantum annealing studies is solvable in polynomial time using digital memcomputing machines, which utilize a collection of dynamical components with memory to represent the structure of the underlying optimization problem. To illustrate the role of memory and clarify the structure of these solvers we propose a simple model of these machines that demonstrates the emergence of long-range order. This model, when applied to finding the ground state of the Ising frustrated-loop benchmarks, undergoes a transient phase of avalanches which can span the entire lattice and demonstrates a connection between long-range behavior and their probability of success. These results establish the advantages of computational approaches based on collective dynamics of continuous dynamical systems

Behavioral synthesis from VHDL using structured modeling

This dissertation describes work in behavioral synthesis involving the development of a VHDL Synthesis System VSS which accepts a VHDL behavioral input specification and performs technology independent synthesis to generate a circuit netlist of generic components. The VHDL language is used for input and output descriptions. An intermediate representation which incorporates signal typing and component attributes simplifies compilation and facilitates design optimization.A Structured Modeling methodology has been developed to suggest standard VHDL modeling practices for synthesis. Structured modeling provides recommendations for the use of available VHDL description styles so that optimal designs will be synthesized.A design composed of generic components is synthesized from the input description through a process of Graph Compilation, Graph Criticism, and Design Compilation. Experiments were performed to demonstrate the effects of different modeling styles on the quality of the design produced by VSS. Several alternative VHDL models were examined for each benchmark, illustrating the improvements in design quality achieved when Structured Modeling guidelines were followed

Transistor-Level Layout of Integrated Circuits

In this dissertation, we present the toolchain BonnCell and its underlying algorithms. It has been developed in close cooperation with the IBM Corporation and automatically generates the geometry for functional groups of 2 to approximately 50 transistors. Its input consists of a set of transistors, including properties like their sizes and their types, a specification of their connectivity, and parameters to flexibly control the technological framework as well as the algorithms' behavior. Using this data, the tool computes a detailed geometric realization of the circuit as polygonal shapes on 16 layers. To this end, a placement routine configures the transistors and arranges them in the plane, which is the main subject of this thesis. Subsequently, a routing engine determines wires connecting the transistors to ensure the circuit's desired functionality. We propose and analyze a family of algorithms that arranges sets of transistors in the plane such that a multi-criteria target function is optimized. The primary goal is to obtain solutions that are as compact as possible because chip area is a valuable resource in modern techologies. In addition to the core algorithms we formulate variants that handle particularly structured instances in a suitable way. We will show that for 90% of the instances in a representative test bed provided by IBM, BonnCell succeeds to generate fully functional layouts including the placement of the transistors and a routing of their interconnections. Moreover, BonnCell is in wide use within IBM's groups that are concerned with transistor-level layout - a task that has been performed manually before our automation was available. Beyond the processing of isolated test cases, two large-scale examples for applications of the tool in the industry will be presented: On the one hand the initial design phase of a large SRAM unit required only half of the expected 3 month period, on the other hand BonnCell could provide valuable input aiding central decisions in the early concept phase of the new 14 nm technology generation

Subclasses of Presburger Arithmetic and the Weak EXP Hierarchy

It is shown that for any fixed $i>0$, the $\Sigma_{i+1}$-fragment of Presburger arithmetic, i.e., its restriction to $i+1$ quantifier alternations beginning with an existential quantifier, is complete for $\mathsf{\Sigma}^{\mathsf{EXP}}_{i}$, the $i$-th level of the weak EXP hierarchy, an analogue to the polynomial-time hierarchy residing between $\mathsf{NEXP}$ and $\mathsf{EXPSPACE}$. This result completes the computational complexity landscape for Presburger arithmetic, a line of research which dates back to the seminal work by Fischer & Rabin in 1974. Moreover, we apply some of the techniques developed in the proof of the lower bound in order to establish bounds on sets of naturals definable in the $\Sigma_1$-fragment of Presburger arithmetic: given a $\Sigma_1$-formula $\Phi(x)$, it is shown that the set of non-negative solutions is an ultimately periodic set whose period is at most doubly-exponential and that this bound is tight.Comment: 10 pages, 2 figure

Logical strength of complexity theory and a formalization of the PCP theorem in bounded arithmetic

We present several known formalizations of theorems from computational complexity in bounded arithmetic and formalize the PCP theorem in the theory PV1 (no formalization of this theorem was known). This includes a formalization of the existence and of some properties of the (n,d,{\lambda})-graphs in PV1

On embeddings of CAT(0) cube complexes into products of trees

We prove that the contact graph of a 2-dimensional CAT(0) cube complex ${\bf X}$ of maximum degree $\Delta$ can be coloured with at most $\epsilon(\Delta)=M\Delta^{26}$ colours, for a fixed constant $M$. This implies that ${\bf X}$ (and the associated median graph) isometrically embeds in the Cartesian product of at most $\epsilon(\Delta)$ trees, and that the event structure whose domain is ${\bf X}$ admits a nice labeling with $\epsilon(\Delta)$ labels. On the other hand, we present an example of a 5-dimensional CAT(0) cube complex with uniformly bounded degrees of 0-cubes which cannot be embedded into a Cartesian product of a finite number of trees. This answers in the negative a question raised independently by F. Haglund, G. Niblo, M. Sageev, and the first author of this paper.Comment: Some small corrections; main change is a correction of the computation of the bounds in Theorem 1. Some figures repaire