Temperature and voltage measurement for field test using an Aging-Tolerant monitor

Measuring temperature and voltage (T&V) in a current VLSI is very important in guaranteeing its reliability, because a large variation of temperature or voltage in field will reduce a delay margin and makes the chip behavior unreliable. This paper proposes a novel method of T&V measurement, which can be used for variety of applications, such as field test, online test, or hot-spot monitoring. The method counts frequencies of more than one ring oscillator (RO), which composes an aging-tolerant monitor. Then, the T&V are derived from the frequencies using a multiple regression analysis. To improve the accuracy of measurement, three techniques of an optimal selection of RO types, their calibration, and hierarchical calculation are newly introduced. In order to make sure the proposed method, circuit simulation in 180-, 90-, and 45-nm CMOS technologies is performed. In the 180-nm CMOS technology, the temperature accuracy is within 0.99 °C, and the voltage accuracy is within 4.17 mV. Furthermore, some experimental results using fabricated test chips with 180-nm CMOS technology confirm its feasibility

On-Line Stability Detectors for Sequential Circuit Elements

I conducted this study of on-line stability detectors to learn more about stability checking in VLSI circuitry and how I varied the conditions in order to try to find trends on how well the stability detectors work each set of conditions. I varied the clock speed, temperature, transistor feature size, and sizing of the transistors in both Franco’s Stability Checker and Yada’s MSC Cell from papers [3] and [5] respectively. I found that the sizing has the greatest impact on both test stability detectors and that both stability detectors can work under a variety of conditions with little to no loss in functionality. I did notice, however, that in general lower temperatures and smaller feature sizes produce better performance under most conditions. For Franco’s detector, a smaller error pullup transistor results in better error detection while a larger pullup transistor allows for better setup times. For the MSC Cell, smaller transistors resulted in better performance

On-chip test clock validation using a time-to-digital converter in FPGAs

While on-chip delay measurement combining logic BIST with a variable test clock is an effective way to secure field reliability of VLSI/FPGAs, validation of the variable test clock generated on the chip is important to guarantee measurement accuracy. This paper addresses a method of on-chip test clock validation using a TDC (Time-to-Digital Converter) for FPGAs. The proposed method has two operation modes, one is a resolution measurement mode and the other is a phase difference measurement mode. The resolution measurement mode is performed first to check the resolution of the TDC circuit. The phase difference measurement mode checks the timing difference between the original clock and the generated test clock. Evaluation experiments using a real FPGA device shows that the resolution of the proposed clock validation method using a TDC is 50.46 ps. For a variable test clock with resolution of 96.15 ps, it was confirmed that INL (Integral Non-Linearity) of the clock is within 10% and it was inconsistent with a result observed by an oscilloscope.The 3rd International Test Conference in Asia (ITC-Asia 2019), September 3-5, 2019Tokyo Denki University, Tokyo, Japa

On-chip delay measurement for in-field test of FPGAs

Avoidance of delay-related failures due to aging phenomena is an important issue of current VLSI systems. Delay measurement in field is effective for detection of aging-induced delay increase. This paper proposes a delay measurement method using BIST (Built-In Self-Test) in an FPGA. The proposed method consists of variable test timing generation using an embedded PLL, BIST-based delay measurement, and correction of the measured delay with reflecting temperature variance in field. In on-chip delay measurement of the proposed method, the fastest operating speed is checked by repeating delay test with several test timings. Because circuit delay is influenced by temperature during measurement, the measured delay is then corrected according to the temperature during testing. Based on test log including the corrected delay, delay degradation and aging detection can be grasped. In evaluation experiments of the propose method implemented on an Intel Cyclone IV FPGA device (60nm technology), variable test timing generation realized 96 ps timing step resolution (that is below 1% of the system clock), correction process for measured delay could reduce influence of temperature variation. Furthermore, its feasibility of the proposed method for aging detection is discussed in this paper.24th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2019), December 1-3, 2019, Kyoto, Japa

Integrated Circuit Design for Radiation Sensing and Hardening.

Beyond the 1950s, integrated circuits have been widely used in a number of electronic devices surrounding people’s lives. In addition to computing electronics, scientific and medical equipment have also been undergone a metamorphosis, especially in radiation related fields where compact and precision radiation detection systems for nuclear power plants, positron emission tomography (PET), and radiation hardened by design (RHBD) circuits for space applications fabricated in advanced manufacturing technologies are exposed to the non-negligible probability of soft errors by radiation impact events. The integrated circuit design for radiation measurement equipment not only leads to numerous advantages on size and power consumption, but also raises many challenges regarding the speed and noise to replace conventional design modalities. This thesis presents solutions to front-end receiver designs for radiation sensors as well as an error detection and correction method to microprocessor designs under the condition of soft error occurrence. For the first preamplifier design, a novel technique that enhances the bandwidth and suppresses the input current noise by using two inductors is discussed. With the dual-inductor TIA signal processing configuration, one can reduce the fabrication cost, the area overhead, and the power consumption in a fast readout package. The second front-end receiver is a novel detector capacitance compensation technique by using the Miller effect. The fabricated CSA exhibits minimal variation in the pulse shape as the detector capacitance is increased. Lastly, a modified D flip-flop is discussed that is called Razor-Lite using charge-sharing at internal nodes to provide a compact EDAC design for modern well-balanced processors and RHBD against soft errors by SEE.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/111548/1/iykwon_1.pd

Synthesis for circuit reliability

textElectrical and Computer Engineerin

A Fully-Digital Temperature and Voltage Monitor for Field Teat

VLSI の高機能化や高性能化，製造プロセスの微細化など，半導体製造技術の進歩の一方で，物理的な劣化現象が信頼性に影響を及ぼす重大な要因となっている．そのため，劣化による故障を事前に検知し，障害発生による突然のシステムダウンを回避することが重要となる．劣化の進行はシステムの運用状況に依存するため製造テストでの検出は困難であり，劣化により生じる故障に対しては出荷後のフィールドでのテストが有用である．VLSI の劣化現象として回路遅延の増加が知られているが，遅延値は温度や電圧等の環境要因により変動するため，劣化による遅延増加を測定するには，VLSI 動作時の温度と電圧のモニタリングが必要不可欠となる．温度や電圧のオンチップセンサ技術は様々な手法が提案されている．例えば，一般的な温度センサとして実用化されているサーマルダイオード等を利用した温度センサは高い測定精度を実現できるが，アナログ回路を利用しているため，チップ内でのモニタ配置の物理制約が厳しく，チップのホットスポット把握の為に多数箇所へ搭載することが困難である．他にも様々な手法が提案されているが，これらの温度や電圧センサは，システムを長期間稼動させ続けた際に発生する劣化現象への対策が施されていないなど，フィールドテストに用いるセンサとしては不向きである．本論文では，フィールドにおける高精度なオンチップ温度電圧測定手法を確立させることを目的とし，完全デジタル設計が可能なリングオシレータ(RO: Ring-Oscillator) を核とする温度電圧モニタについて提案する．提案モニタはRO の動作周波数が温度や電圧によって変動する特性を利用する．本論文では，複数種類の特性の異なるRO から構成されるモニタを提案し，各ROの周波数と温度の特性，周波数と電圧の特性に対して，重回帰分析を用いることにより，システム運用時の温度・電圧変動による周波数の変化量からチップ内の温度と電圧が計算可能となることを示す．製造されたVLSI は製造バラツキの影響を受けるため，提案モニタに搭載するRO の動作周波数は製造バラツキの影響を受けて変動し，温度と電圧の測定精度が低下する．製造バラツキの影響により生じる誤差を低減するため，初回測定時における周波数測定値と標準環境での周波数測定値の比率を利用したキャリブレーション手法を提案する．そして，製造バラツキが存在していても，精度良くRO 周波数からチップ内の温度と電圧の測定が可能となることを示す．RO として利用可能な論理回路は様々な種類があり，それらのRO の組合せによって温度と電圧の測定精度が変動する．本論文では，利用可能なRO から温度電圧モニタとして精度の良い3 種類の組合せを選択する手法を提案し，温度と電圧が高精度で測定可能となるROが選択可能なことを示す．提案モニタは完全デジタル設計であるため，標準的なセルライブラリで提供された論理セルだけで構成することができ，設計や製造におけるコストが小さい．また，モニタ自身に対する劣化現象の影響を避けるため，提案モニタを構成するRO は耐NBTI (Negative Bios Temperature Instability) 劣化の構造を実現している．本論文では，180nm と90nm，45nm のCMOS テクノロジを用いた回路シミュレーションを用いて提案手法の測定精度や有効性の評価を行う．180nm CMOS テクノロジにおいて，0～120℃の温度範囲および1.65～1.95V の電圧範囲で，0.99℃の温度測定精度，4.17mV の電圧測定精度を持ち，温度と電圧を同時に測定可能なデジタルモニタであることを示す．また，回路シミュレーションを用いた評価だけでなく，提案モニタを搭載したチップを設計し，試作を行う．試作チップから得られるRO の温度電圧変化特性を測定し，提案手法を適応することで，チップ内の温度と電圧が測定できることを示す．そして，モニタで測定した温度や電圧の測定結果に対する妥当性の評価を行い，温度電圧モニタとして実現可能であることを示す．提案する温度電圧モニタを用いることで短時間測定可能でかつ小規模なモニタを実現でき，チップの高信頼化のみならず，医療用機器やIoT（Internet of Things）機器の環境モニタ等，様々な応用も期待できる．九州工業大学博士学位論文 学位記番号:情工博甲第314号 学位授与年月日:平成28年6月30日第1章 序論|第2章 LSI のテストと信頼性|第3章 リングオシレータを利用した温度電圧測定|第4章 温度電圧モニタ回路|第5章 試作チップによる評価|第6章 結論九州工業大学平成28年