5,559 research outputs found
Channel Characterization for Chip-scale Wireless Communications within Computing Packages
Wireless Network-on-Chip (WNoC) appears as a promising alternative to
conventional interconnect fabrics for chip-scale communications. WNoC takes
advantage of an overlaid network composed by a set of millimeter-wave antennas
to reduce latency and increase throughput in the communication between cores.
Similarly, wireless inter-chip communication has been also proposed to improve
the information transfer between processors, memory, and accelerators in
multi-chip settings. However, the wireless channel remains largely unknown in
both scenarios, especially in the presence of realistic chip packages. This
work addresses the issue by accurately modeling flip-chip packages and
investigating the propagation both its interior and its surroundings. Through
parametric studies, package configurations that minimize path loss are obtained
and the trade-offs observed when applying such optimizations are discussed.
Single-chip and multi-chip architectures are compared in terms of the path loss
exponent, confirming that the amount of bulk silicon found in the pathway
between transmitter and receiver is the main determinant of losses.Comment: To be presented 12th IEEE/ACM International Symposium on
Networks-on-Chip (NOCS 2018); Torino, Italy; October 201
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
Near-sensor data analytics is a promising direction for IoT endpoints, as it
minimizes energy spent on communication and reduces network load - but it also
poses security concerns, as valuable data is stored or sent over the network at
various stages of the analytics pipeline. Using encryption to protect sensitive
data at the boundary of the on-chip analytics engine is a way to address data
security issues. To cope with the combined workload of analytics and encryption
in a tight power envelope, we propose Fulmine, a System-on-Chip based on a
tightly-coupled multi-core cluster augmented with specialized blocks for
compute-intensive data processing and encryption functions, supporting software
programmability for regular computing tasks. The Fulmine SoC, fabricated in
65nm technology, consumes less than 20mW on average at 0.8V achieving an
efficiency of up to 70pJ/B in encryption, 50pJ/px in convolution, or up to
25MIPS/mW in software. As a strong argument for real-life flexible application
of our platform, we show experimental results for three secure analytics use
cases: secure autonomous aerial surveillance with a state-of-the-art deep CNN
consuming 3.16pJ per equivalent RISC op; local CNN-based face detection with
secured remote recognition in 5.74pJ/op; and seizure detection with encrypted
data collection from EEG within 12.7pJ/op.Comment: 15 pages, 12 figures, accepted for publication to the IEEE
Transactions on Circuits and Systems - I: Regular Paper
The "MIND" Scalable PIM Architecture
MIND (Memory, Intelligence, and Network Device) is an advanced parallel computer architecture for high performance computing and scalable embedded processing. It is a
Processor-in-Memory (PIM) architecture integrating both DRAM bit cells and CMOS logic devices on the same silicon die. MIND is multicore with multiple memory/processor nodes on
each chip and supports global shared memory across systems of MIND components. MIND is distinguished from other PIM architectures in that it incorporates mechanisms for efficient support of a global parallel execution model based on the semantics of message-driven multithreaded split-transaction processing. MIND is designed to operate either in conjunction with other conventional microprocessors or in standalone arrays of like devices. It also incorporates mechanisms for fault tolerance, real time execution, and active power management. This paper describes the major elements and operational methods of the MIND
architecture
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