Low-power reconfigurable network architecture for on-chip photonic interconnects

Photonic Networks-On-Chip have emerged as a viable solution for interconnecting multicore computer architectures in a power-efficient manner. Current architectures focus on large messages, however, which are not compatible with the coherence traffic found on chip multiprocessor networks. In this paper, we introduce a reconfigurable optical interconnect in which the topology is adapted automatically to the evolving traffic situation. This allows a large fraction of the (short) coherence messages to use the optical links, making our technique a better match for CMP networks when compared to existing solutions. We also evaluate the performance and power efficiency of our architecture using an assumed physical implementation based on ultra-low power optical switching devices and under realistic traffic load conditions

Towards a low-power nanophotonic semiconductor amplifier heterogeneously integrated with SOI waveguides

In this paper we propose an optically pumped nanophotonic III-V semiconductor optical amplifier heterogeneously integrated on a silicon-on-insulator waveguide circuit through wafer bonding technology. 10 μ m long adiabatic tapers allow a full power transfer from the silicon waveguide layer to the III-V membrane. Low-power consumption is expected, given the high optical confinement in the 100nm thick III-V membrane waveguide, making it suitable for intra-chip optical interconnect networks. We report on the design and preliminary characterization of this novel type of high-index contrast nanophotonic device

Hydrogenated amorphous silicon photonics

Silicon Photonics is quickly proving to be a suitable interconnect technology for meeting the future goals of on-chip bandwidth and low power requirements. However, it is not clear how silicon photonics will be integrated into CMOS chips, particularly microprocessors. The issue of integrating photonic circuits into electronic IC fabrication processes to achieve maximum flexibility and minimize complexity and cost is an important one. In order to maximize usage of chip real estate, it will be advantageous to integrate in three-dimensions. Hydrogenated-amorphous silicon (a-Si:H) is emerging as a promising material for the 3-D integration of silicon photonics for on-chip optical interconnects. In addition, a-Si:H film can be deposited using CMOS compatible low temperature plasma-enhanced chemical vapor deposition (PECVD) process at any point in the fabrication process allowing vertical stacking of optical interconnects. In this thesis we demonstrate a-Si:H as a high performance alternate platform to crystalline silicon, enabling backend integration of optical interconnects in a hybrid photonic-electronic network-on-chip architecture. High quality passive devices are fabricated on a low-loss a-Si:H platform enabling wavelength division multiplexing schemes. We demonstrate a broadband all-optical modulation scheme based on free-carrier absorption effect, which can enable compact electro-optic modulators in a-Si:H. Furthermore, we comprehensively characterize the optical nonlinearities in a-Si:H and observe that a-Si:H exhibits enhanced nonlinearities as compared to crystalline silicon. Based on the enhanced nonlinearities, we demonstrate low-power four-wave mixing in a-Si:H waveguides enabling high-speed all-optical devices in an a-Si:H platform. Finally, we demonstrate a novel data encoding scheme using thermal and all-optical tuning of silicon waveguides, increasing the spectral efficiency in an interconnect link. Looking forward, we shall also discuss some of the challenges that still need to be overcome to realize an integrated a-Si:H based photonic link

Photonic integration enabling new multiplexing concepts in optical board-to-board and rack-to-rack interconnects

New broadband applications are causing the datacenters to proliferate, raising the bar for higher interconnection speeds. So far, optical board-to-board and rack-to-rack interconnects relied primarily on low-cost commodity optical components assembled in a single package. Although this concept proved successful in the first generations of optical-interconnect modules, scalability is a daunting issue as signaling rates extend beyond 25 Gb/s. In this paper we present our work towards the development of two technology platforms for migration beyond Infiniband enhanced data rate (EDR), introducing new concepts in board-to-board and rack-to-rack interconnects. The first platform is developed in the framework of MIRAGE European project and relies on proven VCSEL technology, exploiting the inherent cost, yield, reliability and power consumption advantages of VCSELs. Wavelength multiplexing, PAM-4 modulation and multi-core fiber (MCF) multiplexing are introduced by combining VCSELs with integrated Si and glass photonics as well as BiCMOS electronics. An in-plane MCF-to-SOI interface is demonstrated, allowing coupling from the MCF cores to 340x400 nm Si waveguides. Development of a low-power VCSEL driver with integrated feed-forward equalizer is reported, allowing PAM-4 modulation of a bandwidth-limited VCSEL beyond 25 Gbaud. The second platform, developed within the frames of the European project PHOXTROT, considers the use of modulation formats of increased complexity in the context of optical interconnects. Powered by the evolution of DSP technology and towards an integration path between inter and intra datacenter traffic, this platform investigates optical interconnection system concepts capable to support 16QAM 40GBd data traffic, exploiting the advancements of silicon and polymer technologies

Integrated GHz silicon photonic interconnect with micrometer-scale modulators and detectors

We report an optical link on silicon using micrometer-scale ring-resonator enhanced silicon modulators and waveguide-integrated germanium photodetectors. We show 3 Gbps operation of the link with 0.5 V modulator voltage swing and 1.0 V detector bias. The total energy consumption for such a link is estimated to be ~120 fJ/bit. Such compact and low power monolithic link is an essential step towards large-scale on-chip optical interconnects for future microprocessors

Cycle-accurate evaluation of reconfigurable photonic networks-on-chip

There is little doubt that the most important limiting factors of the performance of next-generation Chip Multiprocessors (CMPs) will be the power efficiency and the available communication speed between cores. Photonic Networks-on-Chip (NoCs) have been suggested as a viable route to relieve the off- and on-chip interconnection bottleneck. Low-loss integrated optical waveguides can transport very high-speed data signals over longer distances as compared to on-chip electrical signaling. In addition, with the development of silicon microrings, photonic switches can be integrated to route signals in a data-transparent way. Although several photonic NoC proposals exist, their use is often limited to the communication of large data messages due to a relatively long set-up time of the photonic channels. In this work, we evaluate a reconfigurable photonic NoC in which the topology is adapted automatically (on a microsecond scale) to the evolving traffic situation by use of silicon microrings. To evaluate this system's performance, the proposed architecture has been implemented in a detailed full-system cycle-accurate simulator which is capable of generating realistic workloads and traffic patterns. In addition, a model was developed to estimate the power consumption of the full interconnection network which was compared with other photonic and electrical NoC solutions. We find that our proposed network architecture significantly lowers the average memory access latency (35% reduction) while only generating a modest increase in power consumption (20%), compared to a conventional concentrated mesh electrical signaling approach. When comparing our solution to high-speed circuit-switched photonic NoCs, long photonic channel set-up times can be tolerated which makes our approach directly applicable to current shared-memory CMPs

Devices Having Compliant Wafer-level Input/output Interconnections And Packages Using Pillars And Methods Of Fabrication Thereof

Devices having one or more of the following: an input/output (I/O) interconnect system, an optical I/O interconnect, an electrical I/O interconnect, a radio frequency I/O interconnect, are disclosed. A representative I/O interconnect system includes a first substrate and a second substrate. The first substrate includes a compliant pillar vertically extending from the first substrate. The compliant pillar is constructed of a first material. The second substrate includes a compliant socket adapted to receive the compliant pillar. The compliant socket is constructed of a second material.Georgia Tech Research Corporatio