Efficient hardware architecture for fast IP address lookup

A multigigabit IP router may receive several millions packets per second from each input link. For each packet, the router needs to find the longest matching prefix in the forwarding table in order to determine the packet's next-hop. In this paper, we present an efficient hardware solution for the IP address lookup problem. We model the address lookup problem as a searching problem on a binary-trie. The binary-trie is partitioned into four levels of fixed size 255-node subtrees. We employ a hierarchical indexing structure to facilitate direct access to subtrees in a given level. It is estimated that a forwarding table with 40K prefixes will consume 2.5Mbytes of memory. The searching is implemented using a hardware pipeline with a minimum cycle of 12.5ns if the memory modules are implemented using SRAM. A distinguishing feature of our design is that forwarding table entries are not replicated in the data structure. Hence, table updates can be done in constant time with only a few memory accesses.published_or_final_versio

Design and implementation of high speed multimedia network.

by Yeung Chung Toa.Thesis (M.Phil.)--Chinese University of Hong Kong, 1994.Includes bibliographical references (leaves 63-[65]).Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Bandwidth required by multimedia applications --- p.1Chapter 1.2 --- Real-time requirement --- p.2Chapter 1.3 --- Multicasting --- p.2Chapter 1.4 --- Other networks --- p.3Chapter 1.5 --- Overview of CUM LAUDE NET --- p.5Chapter 1.5.1 --- Protocols --- p.7Chapter 1.5.2 --- Network Services --- p.8Chapter 1.6 --- Scope of the Thesis --- p.9Chapter 2 --- Network Architecture --- p.11Chapter 2.1 --- CUM LAUDE NET Architectural Overview --- p.11Chapter 2.2 --- Level One Network Architecture --- p.12Chapter 2.3 --- Level-One Router --- p.14Chapter 2.3.1 --- packet forwarding --- p.14Chapter 2.3.2 --- packet insertion --- p.15Chapter 2.3.3 --- packet removal --- p.15Chapter 2.3.4 --- fault protection --- p.15Chapter 2.4 --- Hub --- p.16Chapter 2.5 --- Host & Network Interface Card --- p.17Chapter 3 --- Protocol --- p.19Chapter 3.1 --- Design Overview --- p.19Chapter 3.2 --- Layering --- p.20Chapter 3.3 --- "Segment, Datagram, and Packet Format" --- p.21Chapter 3.3.1 --- IP/VCI field --- p.23Chapter 3.4 --- Data Link --- p.23Chapter 3.4.1 --- byte format and data link synchronization --- p.23Chapter 3.4.2 --- access control byte --- p.24Chapter 3.4.3 --- packet/frame boundary --- p.26Chapter 3.5 --- Fast Packet Routing Protocol --- p.26Chapter 3.5.1 --- Level-2/Level-l Bridge/Router --- p.27Chapter 3.5.2 --- Level-1 Hub --- p.29Chapter 3.5.3 --- Local Host NIC --- p.29Chapter 3.6 --- Media Access Control Protocol I : ACTA --- p.30Chapter 3.7 --- Media Access Control Protocol II: Hub Polling --- p.34Chapter 3.8 --- Protocol Implementation on CUM LAUDE NET --- p.36Chapter 4 --- Hardware Implementation & Performance of Routers and NIC --- p.40Chapter 4.1 --- Functionality of Router --- p.40Chapter 4.2 --- Important Components Used in the Router Design --- p.43Chapter 4.2.1 --- TAXI Transmitter and Receiver --- p.43Chapter 4.2.2 --- First-In-First-Out Memory (FIFO) --- p.44Chapter 4.3 --- Design of Router --- p.45Chapter 4.3.1 --- Version 1 --- p.45Chapter 4.3.2 --- Version 2 --- p.47Chapter 4.3.3 --- Version 3 --- p.50Chapter 4.4 --- Lessons Learned from the High Speed Router Design --- p.57Chapter 5 --- Conclusion --- p.61Bibliography --- p.6

MLET: A Power Efficient Approach for TCAM Based, IP Lookup Engines in Internet Routers

Routers are one of the important entities in computer networks specially the Internet. Forwarding IP packets is a valuable and vital function in Internet routers. Routers extract destination IP address from packets and lookup those addresses in their own routing table. This task is called IP lookup. Internet address lookup is a challenging problem due to the increasing routing table sizes. Ternary Content-Addressable Memories (TCAMs) are becoming very popular for designing high-throughput address lookup-engines on routers: they are fast, cost-effective and simple to manage. Despite the TCAMs speed, their high power consumption is their major drawback. In this paper, Multilevel Enabling Technique (MLET), a power efficient TCAM based hardware architecture has been proposed. This scheme is employed after an Espresso-II minimization algorithm to achieve lower power consumption. The performance evaluation of the proposed approach shows that it can save considerable amount of routing table's power consumption.Comment: 14 Pages, IJCNC 201

Generación de flujos en redes multigigabit ethernet acelerada mediante hardware dedicado

The extended use of the network has made the Internet companies change their strategy about how to analyze their links. On the one hand, the need of more powerful computers and servers arise, which, in turn, increases the economic cost. In order to avoid the use of high-performance devices, arquitectures based on commodity hardware along with FPGAs are sought. On the other hand, they need to characterize the use of their network traffic links to improve the quality of their service and to detect problems or malicious attacks. For that, they analyze the traffic they deal with. Studying it from the point of view of each individual packet results in an infeasible task, for it does not contribute sufficient useful information. The optimum aggregation level for this task on multigigabit links is found to reside in the analysis on the flow level, in which each flow represents a unidirectional connection between two Internet users. A hybrid system composed of both dedicated hardware and software is presented in this Graduate Project. The developed hardware component is able to capture and analyze the totality of the traffic up to 10 Gbps and 14 Mpps, as well as to classify the packets in subnetworks with no information loss whatsoever. The software subsystem is able to produce its own flows associated with the traffic through the use of the hardware-produced data, with the use of no more than two of the cores of a conventional CPU. These good outcomes are due to the use of DMA transferences. The complete development of this project has been possible thanks to the utilization of HLS tools. Otherwise, it would not have been possible to codify the totality of the project. The hardware development methodology has entailed a realist strategy, technologically and economically oriented, because not only the cost of the FPGA used, but the development time as well have been proportional to the proposed objectives of this project.El extendido uso de la red en la actualidad ha significado que las empresas de Internet cambien su estrategia en el análisis de sus enlaces. Por un lado, surge la necesidad de utilizar equipos cada vez más potentes, lo que implica un aumento en el coste. Para evitar el uso de dispositivos de alto rendimiento, se buscan arquitecturas basadas en commodity hardware junto con FPGAs. Por otro lado, necesitan caracterizar el uso de sus enlaces para mejorar la calidad de sus servicios y detectar problemas o posibles ataques maliciosos. Para ello realizan un análisis del tráfico que manejan. Estudiar éste a nivel de cada paquete individual es inviable y no aporta la suficiente información relevante. El nivel de agregación óptimo para esta tarea en enlaces multigigabit reside en el análisis a nivel de flujos, donde cada flujo representará una conexión unidireccional entre dos usuarios de Internet. En este Trabajo de Fin de Grado se presenta un sistema híbrido que integra hardware dedicado con software. El módulo hardware desarrollado es capaz de capturar y analizar el 100% del tráfico a 10 Gbps y 14 Mpps, así como de clasificar los paquetes en subredes sin que se produzca pérdida de información. El subsistema software es capaz de generar los flujos asociados al tráfico mediante la transferencia de los datos generados en hardware, sin utilizar más de dos núcleos de un procesador convencional, gracias al uso de transferencias DMA. El desarrollo completo de este proyecto ha sido posible, en cuanto al tiempo dedicado a la codificación, gracias al uso de herramientas HLS. La metodología de desarrollo hardware ha supuesto una estrategia realista en términos tecno-económicos ya que tanto el coste de la FPGA utilizada como el tiempo de desarrollo han sido acordes con los objetivos propuestos en este trabajo

A DRAM/SRAM memory scheme for fast packet buffers

We address the design of high-speed packet buffers for Internet routers. We use a general DRAM/SRAM architecture for which previous proposals can be seen as particular cases. For this architecture, large SRAMs are needed to sustain high line rates and a large number of interfaces. A novel algorithm for DRAM bank allocation is presented that reduces the SRAM size requirements of previously proposed schemes by almost an order of magnitude, without having memory fragmentation problems. A technological evaluation shows that our design can support thousands of queues for line rates up to 160 Gbps.Peer ReviewedPostprint (published version

Can Software Routers Scale?

Software routers can lead us from a network of special-purpose hardware routers to one of general-purpose extensible infrastructure--if, that is, they can scale to high speeds. We identify the challenges in achieving this scalability and propose a solution: a cluster-based router architecture that uses an interconnect of commodity server platforms to build software routers that are both incrementally scalable and fully programmable

Flexible LDPC Decoder Architectures

Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption