Reliability analysis of triple modular redundancy system with spare

Hardware redundant fault-tolerant systems and the different design approaches are discussed. The reliability analysis of fault-tolerant systems is usually done under permanent fault conditions. With statistical data suggesting that up to 90% of system failures are caused by intermittent faults, the reliability analysis of fault-tolerant systems must concentrate more on this class of faults. In this work, a reconfigurable Triple Modular Redundancy (TMR) with spare system that differentiates between permanent and intermittent faults has been built. The reconfiguration process of this system depends on both the current status of its modules and their history. Based on this, a different approach for reliability analysis under intermittent fault conditions using Markov models is presented. This approach shows a much higher system reliability compared to other redundant and non-redundant configurations

Logic simulation on a cellular automata machine

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 1997.Includes bibliographical references (p. 210-214).by Ruben AginM.Eng

Public key cryptosystems : theory, application and implementation

The determination of an individual's right to privacy is mainly a nontechnical matter, but the pragmatics of providing it is the central concern of the cryptographer. This thesis has sought answers to some of the outstanding issues in cryptography. In particular, some of the theoretical, application and implementation problems associated with a Public Key Cryptosystem (PKC).The Trapdoor Knapsack (TK) PKC is capable of fast throughput, but suffers from serious disadvantages. In chapter two a more general approach to the TK-PKC is described, showing how the public key size can be significantly reduced. To overcome the security limitations a new trapdoor was described in chapter three. It is based on transformations between the radix and residue number systems.Chapter four considers how cryptography can best be applied to multi-addressed packets of information. We show how security or communication network structure can be used to advantage, then proposing a new broadcast cryptosystem, which is more generally applicable.Copyright is traditionally used to protect the publisher from the pirate. Chapter five shows how to protect information when in easily copyable digital format.Chapter six describes the potential and pitfalls of VLSI, followed in chapter seven by a model for comparing the cost and performance of VLSI architectures. Chapter eight deals with novel architectures for all the basic arithmetic operations. These architectures provide a basic vocabulary of low complexity VLSI arithmetic structures for a wide range of applications.The design of a VLSI device, the Advanced Cipher Processor (ACP), to implement the RSA algorithm is described in chapter nine. It's heart is the modular exponential unit, which is a synthesis of the architectures in chapter eight. The ACP is capable of a throughput of 50 000 bits per second

Fault tolerant programmable digital attitude control electronics study

The attitude control electronics mechanization study to develop a fault tolerant autonomous concept for a three axis system is reported. Programmable digital electronics are compared to general purpose digital computers. The requirements, constraints, and tradeoffs are discussed. It is concluded that: (1) general fault tolerance can be achieved relatively economically, (2) recovery times of less than one second can be obtained, (3) the number of faulty behavior patterns must be limited, and (4) adjoined processes are the best indicators of faulty operation

A survey of DA techniques for PLD and FPGA based systems

Programmable logic devices (PLDs) are gaining in acceptance, of late, for designing systems of all complexities ranging from glue logic to special purpose parallel machines. Higher densities and integration levels are made possible by the new breed of complex PLDs and FPGAs. The added complexities of these devices make automatic computer aided tools indispensable for achieving good performance and a high usable gate-count. In this article, we attempt to present in an unified manner, the different tools and their underlying algorithms using an example of a vending machine controller as an illustrative example. Topics covered include logic synthesis for PLDs and FPGAs along with an in-depth survey of important technology mapping, partitioning and place and route algorithms for different FPGA architectures.Peer Reviewedhttp://deepblue.lib.umich.edu/bitstream/2027.42/31206/1/0000108.pd

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2

Light-Weight Structural Optimization Through Biomimicry, Machine Learning, and Inverse Design

In load-bearing lightweight architectures, cellular materials were frequently utilized. While octahedron, tetrahedron, and octet truss lattice truss were built for lightweight architectures with stretching and flexural dominance, it can be believed that new cells could easily be designed that might perform much better than the present ones in terms of mechanical and architectural characteristics. Machine learning-based structure scouting and design improvisation for better mechanical performance is a growing field of study. Additionally, biomimicry—the science of imitating nature’s elements—offers people a wealth of resources from which to draw motivation as they work to create a better quality of life. Here, utilizing machine learning approaches, novel lattice truss unit cellular architectures with enhanced architectural characteristics were designed. An inverse design methodology employing generative adversarial networks is suggested to investigate and improvise the lightweight lattice truss unit cellular architectures. The proposed framework was utilized to identify various lattice truss unit cellular architectures with load carrying capacities 40–120% greater than those of octet unit cells. A further 130–160% raise in buckling load bearing capacity was made possible by substituting porous biomimicry columns for the solid trusses in the light-weight lattice truss unit cellular architectures. This dissertation\u27s main goal is to investigate various improvisation strategies for creating lightweight architectures, particularly when using data analysis and machine learning methods. Lightweight cellular architectures with thin-walls and lattice truss unit cellular architectures with improved shape memory capabilities were created using the knowledge gleaned from numerous of the research projects mentioned in the preceding paragraphs load-bearing architectures and devices, lightweight architecture with shape memory and with better strength, better stretchability, and better elastic stress recovery are widely desired. As compared to the bulk shape memory polymeric cylinders, the cellular architectures with thin walls show 200% betterer elastic stress recovery that is normalized with respect to base designs. The architectural improvisation of many other additional designs and practical implementation can be accomplished using the inverse design framework

Propulsion Controls, 1979

The state of the art of multivariable engine control is examined in order to determine future needs and problem areas and to establish the appropriate roles of government, industries, and universities in addressing these problems