Efficient Path Delay Test Generation with Boolean Satisfiability

This dissertation focuses on improving the accuracy and efficiency of path delay test generation using a Boolean satisfiability (SAT) solver. As part of this research, one of the most commonly used SAT solvers, MiniSat, was integrated into the path delay test generator CodGen. A mixed structural-functional approach was implemented in CodGen where longest paths were detected using the K Longest Path Per Gate (KLPG) algorithm and path justification and dynamic compaction were handled with the SAT solver. Advanced techniques were implemented in CodGen to further speed up the performance of SAT based path delay test generation using the knowledge of the circuit structure. SAT solvers are inherently circuit structure unaware, and significant speedup can be availed if structure information of the circuit is provided to the SAT solver. The advanced techniques explored include: Dynamic SAT Solving (DSS), Circuit Observability Don’t Care (Cir-ODC), SAT based static learning, dynamic learnt clause management and Approximate Observability Don’t Care (ACODC). Both ISCAS 89 and ITC 99 benchmarks as well as industrial circuits were used to demonstrate that the performance of CodGen was significantly improved with MiniSat and the use of circuit structure

Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy

The operating clock frequency is determined by the longest signal propagation delay, setup/hold time, and timing margin. These are becoming less predictable with the increasing design complexity and process miniaturization. The difficult challenge is then to ensure that a device operating at its clock frequency is error-free with quantifiable assurance. Effort at device-level engineering will not suffice for these circuits exhibiting wide process variation and heightened sensitivities to operating condition stress. Logic-level redress of this issue is a necessity and we propose a design-level remedy for this timing-uncertainty problem. The aim of the design and analysis approaches presented in this dissertation is to provide framework, SABRE, wherein an increased operating clock frequency can be achieved. The approach is a combination of analytical modeling, experimental analy- sis, hardware /time-redundancy design, exception handling and recovery techniques. Our proposed design replicates only a necessary part of the original circuit to avoid high hardware overhead as in triple-modular-redundancy (TMR). The timing-critical combinational circuit is path-wise partitioned into two sections. The combinational circuits associated with long paths are laid out without any intrusion except for the fan-out connections from the first section of the circuit to a replicated second section of the combinational circuit. Thus only the second section of the circuit is replicated. The signals fanning out from the first section are latches, and thus are far shorter than the paths spanning the entire combinational circuit. The replicated circuit is timed at a subsequent clock cycle to ascertain relaxed timing paths. This insures that the likelihood of mistiming due to stress or process variation is eliminated. During the subsequent clock cycle, the outcome of the two logically identical, yet time-interleaved, circuit outputs are compared to detect faults. When a fault is detected, the retry sig- nal is triggered and the dynamic frequency-step-down takes place before a pipe flush, and retry is issued. The significant timing overhead associated with the retry is offset by the rarity of the timing violation events. Simulation results on ISCAS Benchmark circuits show that 10% of clock frequency gain is possible with 10 to 20 % of hardware overhead of replicated timing-critical circuit

Optimization of Pseudo Functional Path Delay Test Through Embedded Memories

Traditional automatic test pattern generation achieves high coverage of logic faults in integrated circuits. Automatic test of embedded memory arrays uses built-in self-test. Testing the memories and logic separately does not fully test the critical timing paths that go into or out of memories. Prior research has developed algorithms and software to test the longest paths into and out of embedded memories. However, in this prior work, the test generation time increased superlinearly with memory size. This is contrary to the intuition that the time should rise approximately linearly with memory size. This behavior limits the algorithm to circuits with relatively small memories. The focus of this research is to analyze the time complexity of the algorithm and propose changes to reduce the time required to test circuits with large memories. We use our prior work on pseudo functional K longest path per gate test generation, and the benchmark circuits with embedded memories developed in the prior work. Since the cells within a memory array are not scan cells, a value that is captured in a memory cell must be moved to a scan cell using low-speed coda cycles. This approach will also support the test of any non-scan flip-flop or latch, in addition to embedded memory arrays. In addition to testing the critical timing paths, testing through memories eliminates the logic “shadows” around the memory where faults cannot be tested. In this research our complexity analysis has identified the reason for the superlinear increase in test generation time with larger memories and verified this analysis with experimental results. We have also developed and implemented several heuristics to increase performance, with experimental results. This research also identifies the major algorithm changes required to further increase performance

High Quality Compact Delay Test Generation

Delay testing is used to detect timing defects and ensure that a circuit meets its timing specifications. The growing need for delay testing is a result of the advances in deep submicron (DSM) semiconductor technology and the increase in clock frequency. Small delay defects that previously were benign now produce delay faults, due to reduced timing margins. This research focuses on the development of new test methods for small delay defects, within the limits of affordable test generation cost and pattern count. First, a new dynamic compaction algorithm has been proposed to generate compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting necessary assignments together during test generation. Second, to make this dynamic compaction approach practical for industrial use, a recursive learning algorithm has been implemented to identify more necessary assignments for each path, so that the path-to-test-pattern matching using necessary assignments is more accurate. Third, a realistic low cost fault coverage metric targeting both global and local delay faults has been developed. The metric suggests the test strategy of generating a different number of longest paths for each line in the circuit while maintaining high fault coverage. The number of paths and type of test depends on the timing slack of the paths under this metric. Experimental results for ISCAS89 benchmark circuits and three industry circuits show that the pattern count of KLPG can be significantly reduced using the proposed methods. The pattern count is comparable to that of transition fault test, while achieving higher test quality. Finally, the proposed ATPG methodology has been applied to an industrial quad-core microprocessor. FMAX testing has been done on many devices and silicon data has shown the benefit of KLPG test

Τεχνικές ανίχνευσης και διόρθωσης λαθών χρονισμού για αυξημένη αξιοπιστία ολοκληρωμένων κυκλωμάτων σε νανομετρικές τεχνολογίες

Η κλιμάκωση της τεχνολογίας καθιστά ιδιαίτερα σημαντική την επίδραση των λαθών χρονισμού στα ολοκληρωμένα κυκλώματα μεγάλης πολυπλοκότητας και υψηλής συχνότητας. Οι διακυμάνσεις της κατασκευαστικής διαδικασίας, της τάσης και της θερμοκρασίας οδηγούν σε μεγάλες αποκλίσεις στις καθυστερήσεις, σε επίπεδο συστήματος, οι οποίες υπονομεύουν την αξιοπιστία των κυκλωμάτων. Επίσης, η αλληλεπίδραση μεταξύ των σημάτων, οι διαταραχές στην τροφοδοσία ισχύος και η αντιστατική/επαγωγική πτώση της τάσης στην τροφοδοσία, επηρεάζουν την απόδοση των συστημάτων, αυξάνοντας την συνολική επίπτωση των λαθών χρονισμού. Επιπρόσθετα, μηχανισμοί γήρανσης προκαλούν σταδιακή μείωση της ταχύτητας των κυκλωμάτων κατά τη διάρκεια της λειτουργίας τους. Υπό αυτές τις συνθήκες, είναι προφανές ότι οι τεχνικές που παρέχουν ανεκτικότητα σε λάθη χρονισμού καθίστανται αναγκαίες καθώς προσφέρουν ανθεκτικότητα έναντι των σφαλμάτων χρονισμού και ικανοποιούν τις προδιαγραφές αξιοπιστίας των συστημάτων. Στo πλαίσιο της διατριβής παρουσιάζονται τρεις τεχνικές ταυτόχρονης εν λειτουργία ανίχνευσης και διόρθωσης λαθών χρονισμού οι οποίες συμβάλλουν στην αξιοπιστία των κυκλωμάτων. Με σκοπό την αξιολόγησή τους, οι τρεις τεχνικές εφαρμόστηκαν σε έναν μικροεπεξεργαστή MIPS R2000 32bit με αρχιτεκτονική δομής διοχέτευσης. Τα πειραματικά αποτελέσματα δείχνουν ότι οι προτεινόμενες τεχνικές ανιχνεύουν και διορθώνουν τα επαγόμενα λάθη χρονισμού με χαμηλό κόστος στην κατανάλωση ισχύος και την επιφάνεια πυριτίου.As technology scales down, timing errors are a real concern in high complexity and high frequency integrated circuits. Process, Voltage and Temperature variations lead to large spreads in delay, at the system level, which undermine circuit’s reliability. Moreover, crosstalk, power supply disturbances and resistive IR-drop or inductance IL-drop affect circuit performance increasing the overall impact of timing errors. In addition, aging mechanisms cause gradual speed degradation of the designs over their service life. In this context, it is evident that timing error tolerance techniques are becoming necessary to provide robustness against timing violations and meet system reliability requirements. This thesis presents three concurrent on-line timing error tolerance techniques which enhance circuit’s reliability. To validate the three techniques, they have been applied in the design of a 32-bits MIPS R2000 pipeline microprocessor. The experimental results show that the proposed techniques detect and correct the generated timing errors efficiently with low power consumption and low silicon area overhead

On Test Coverage of Path Delay Faults

We propose a coverage metric and a two-pass test gen-eration method for path delay faults in combinational logic circuits. The coverage is measured for each line with a rising and a falling transition. However, the test criterion is different from that of the slow-to-rise and slow-to-fall transition faults. The test, called “line delay test”, as a path delay test for the longest sensitizable path produc-ing a given transition on the target line. The maximum number of tests (and faults) is limited to twice the num-ber of lines. However, the line delay test criterion resem-bles path delay test and not the gate or transition delay test. Using a two-pass test generation procedure, we begin with a minimal set of longest paths covering all lines and generate tests for them. Fault simulation is used to de-termine the coverage metric. For uncovered lines, an the second pass, several paths of decreasing length are tar-geted. We present a theorem stating that a redundant stuck-at fault makes all path delay faults involving the faulty line untestable for either a rising or falling transi-tion depending on the type of the stuck-at fault. The use of this theorem considerably reduces the effort of delay test generation. We give results on benchmark circuits.