Testing of Level Shifters in Multiple Voltage Designs

The use of multiple voltages for different cores is becoming a widely accepted technique for efficient power management. Level shifters are used as interfaces between voltage domains. Through extensive transistor level simulations of resistive open, bridging and resistive short faults, we have classified the testing of level shifters into PASSIVE and ACTIVE modes. We examine if high test coverage can be achieved in the PASSIVE mode. We consider resistive opens and shorts and show that, for testing purposes, consideration of purely digital fault effects is sufficient. Thus conventional digital DfT can be employed to test level shifters. In all cases, we conclude that using sets of single supply voltages for testing is sufficient

Dynamic Voltage Scaling Aware Delay Fault Testing

The application of Dynamic Voltage Scaling (DVS) to reduce energy consumption may have a detrimental impact on the quality of manufacturing tests employed to detect permanent faults. This paper analyses the influence of different voltage/frequency settings on fault detection within a DVS application. In particular, the effect of supply voltage on different types of delay faults is considered. This paper presents a study of these problems with simulation results. We have demonstrated that the test application time increases as we reduce the test voltage. We have also shown that for newer technologies we do not have to go to very low voltage levels for delay fault testing. We conclude that it is necessary to test at more than one operating voltage and that the lowest operating voltage does not necessarily give the best fault cover

Layout level design for testability strategy applied to a CMOS cell library

The layout level design for testability (LLDFT) rules used here allow to avoid some hard to detect faults or even undetectable faults on a cell library by modifying the cell layout without changing their behavior and achieving a good level of reliability. These rules avoid some open faults or reduce their appearance probability. The main purpose has been to apply that set of LLDFT rules on the cells of the library designed at the Centre Nacional de Microelectronica (CNM) in order to obtain a highly testable cell library. The authors summarize the main results (area overhead and performance degradation) of the application of the LLDFT rules on the cell

A Low-Cost FPGA-Based Test and Diagnosis Architecture for SRAMs

The continues improvement of manufacturing technologies allows the realization of integrated circuits containing an ever increasing number of transistors. A major part of these devices is devoted to realize SRAM blocks. Test and diagnosis of SRAM circuits are therefore an important challenge for improving quality of next generation integrated circuits. This paper proposes a flexible platform for testing and diagnosis of SRAM circuits. The architecture is based on the use of a low cost FPGA based board allowing high diagnosability while keeping costs at a very low leve

Testability enhancement of a basic set of CMOS cells

Testing should be evaluated as the ability of the test patterns to cover realistic faults, and high quality IC products demand high quality testing. We use a test strategy based on physical design for testability (to discover both open and short faults, which are difficult or even impossible to detect). Consequentially, layout level design for testability (LLDFT) rules have been developed, which prevent the faults, or at least reduce the chance of their appearing. The main purpose of this work is to apply a practical set of LLDFT rules to the library cells designed by the Centre Nacional de Microelectrònica (CNM) and obtain a highly testable cell library. The main results of the application of the LLDFT rules (area overheads and performance degradation) are summarized and the results are significant since IC design is highly repetitive; a small effort to improve cell layout can bring about great improvement in design

Case study: Bio-inspired self-adaptive strategy for spike-based PID controller

A key requirement for modern large scale neuromorphic systems is the ability to detect and diagnose faults and to explore self-correction strategies. In particular, to perform this under area-constraints which meet scalability requirements of large neuromorphic systems. A bio-inspired online fault detection and self-correction mechanism for neuro-inspired PID controllers is presented in this paper. This strategy employs a fault detection unit for online testing of the PID controller; uses a fault detection manager to perform the detection procedure across multiple controllers, and a controller selection mechanism to select an available fault-free controller to provide a corrective step in restoring system functionality. The novelty of the proposed work is that the fault detection method, using synapse models with excitatory and inhibitory responses, is applied to a robotic spike-based PID controller. The results are presented for robotic motor controllers and show that the proposed bioinspired self-detection and self-correction strategy can detect faults and re-allocate resources to restore the controller’s functionality. In particular, the case study demonstrates the compactness (~1.4% area overhead) of the fault detection mechanism for large scale robotic controllers.Ministerio de Economía y Competitividad TEC2012-37868-C04-0

A design for testability study on a high performance automatic gain control circuit.

A comprehensive testability study on a commercial automatic gain control circuit is presented which aims to identify design for testability (DfT) modifications to both reduce production test cost and improve test quality. A fault simulation strategy based on layout extracted faults has been used to support the study. The paper proposes a number of DfT modifications at the layout, schematic and system levels together with testability. Guidelines that may well have generic applicability. Proposals for using the modifications to achieve partial self test are made and estimates of achieved fault coverage and quality levels presente

Towards Structural Testing of Superconductor Electronics

Many of the semiconductor technologies are already\ud facing limitations while new-generation data and\ud telecommunication systems are implemented. Although in\ud its infancy, superconductor electronics (SCE) is capable of\ud handling some of these high-end tasks. We have started a\ud defect-oriented test methodology for SCE, so that reliable\ud systems can be implemented in this technology. In this\ud paper, the details of the study on the Rapid Single-Flux\ud Quantum (RSFQ) process are presented. We present\ud common defects in the SCE processes and corresponding\ud test methodologies to detect them. The (measurement)\ud results prove that we are able to detect possible random\ud defects for statistical purposes in yield analysis. This\ud paper also presents possible test methodologies for RSFQ\ud circuits based on defect oriented testing (DOT)

Preliminary results of geological characterization and geochemical monitoring of Sulcis Basin (Sardinia), as a potential CCS site

The Sulcis Basin is an area situated in SW Sardinia (Italy) and is a potential site for the development of CCS in Italy. This paper illustrates the preliminary results of geological characterization of fractured carbonate reservoir (Miliolitico Fm.) and the sealing sequence, composed by clay, marl and volcanic rocks, with a total thickness of more than 900 m. To characterize the reservoircaprock system an extensive structural-geological survey at the outcrop was conducted. It was also performed a study of the geochemical monitoring, to define the baseline conditions, measuring CO2 concentrations and flux in the study site