2,951 research outputs found
Interconnect research influenced
This article shows that Rent's rule can be viewed as a fundamental law of nature with respect to electronic circuits. As there are many interpretations of the rule, this article will shed some light on the core of Rent's rule and the research that has been built on it
Low-Power, High-Speed Transceivers for Network-on-Chip Communication
Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s
Routing for analog chip designs at NXP Semiconductors
During the study week 2011 we worked on the question of how to automate certain aspects of the design of analog chips. Here we focused on the task of connecting different blocks with electrical wiring, which is particularly tedious to do by hand. For digital chips there is a wealth of research available for this, as in this situation the amount of blocks makes it hopeless to do the design by hand. Hence, we set our task to finding solutions that are based on the previous research, as well as being tailored to the specific setting given by NXP.
This resulted in an heuristic approach, which we presented at the end of the
week in the form of a protoype tool. In this report we give a detailed account of the ideas we used, and describe possibilities to extend the approach
HIGH PERFORMANCE CLOCK DISTRIBUTION FOR HIGH-SPEED VLSI SYSTEMS
Tohoku University堀口 進課
A Hierarchical Timing Simulation Model
A hierarchical timing simulation model has been developed
to deal with VLSI designs at any level of representation. A set of physically based parameters are used to characterize the behavior and timing of a semantic design object (cell) independent of its composition
environment. As cells are composed, the parameters of the composite cell can be determined from those of the component cells either analytically
or by simulation. Based on this model, a behavior-level simulator has been developed and combined with other tools to form an integrated design system that fully supports the structured design methodology
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