'Institute of Electrical and Electronics Engineers (IEEE)'
Doi
Abstract
A hierarchical timing simulation model has been developed
to deal with VLSI designs at any level of representation. A set of physically based parameters are used to characterize the behavior and timing of a semantic design object (cell) independent of its composition
environment. As cells are composed, the parameters of the composite cell can be determined from those of the component cells either analytically
or by simulation. Based on this model, a behavior-level simulator has been developed and combined with other tools to form an integrated design system that fully supports the structured design methodology
