Error control for reliable digital data transmission and storage systems

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. In this paper we present some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative alorithm to find the error locator polynomial. Two codes are considered: (1) a d sub min = 4 single-byte-error-correcting (SBEC), double-byte-error-detecting (DBED) RS code; and (2) a d sub min = 6 double-byte-error-correcting (DBEC), triple-byte-error-detecting (TBED) RS code

Integer Codes Correcting Double Errors and Triple-Adjacent Errors Within a Byte

This article presents a class of integer codes that are suitable for use in optical computer networks in which the data are transmitted serially. The presented codes are constructed with the help of a computer and have three desirable properties. First, they use integer and lookup table operations, which make them suitable for software implementation. Second, depending on the application requirements, the proposed codes can be used as low-rate error correction (EC) codes or as high-rate error detection (ED) codes. In the EC mode, which is suited for realtime applications, the receiver can correct all single and double errors, as well as all triple-adjacent (TA) errors within one b-bit byte. On the other hand, if the integrity of data is of high importance, the receiver may operate in the ED mode. In that case, it is able to detect all quadruple errors, all double TA errors within one b-bit byte, and all double TA errors within two b-bit bytes. Finally, it is important to note that the presented codes can be interleaved without delay and without using any additional hardware. Owing to this, it is possible to construct simple codes capable of detecting/correcting multiple TA and random errors.This is the peer-reviewed version of the paper: Radonjic, A., 2020. Integer Codes Correcting Double Errors and Triple-Adjacent Errors Within a Byte. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28, 1901–1908. [https://doi.org/10.1109/TVLSI.2020.2998364]© 20XX IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Published version: [https://hdl.handle.net/21.15107/rcub_dais_9991

Reed Solomon codes for error control in byte organized computer memory systems

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. In LSI and VLSI technology, memories are often organized on a multiple bit (or byte) per chip basis. For example, some 256K-bit DRAM's are organized in 32Kx8 bit-bytes. Byte oriented codes such as Reed Solomon (RS) codes can provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special decoding techniques for extended single-and-double-error-correcting RS codes which are capable of high speed operation are presented. These techniques are designed to find the error locations and the error values directly from the syndrome without having to use the iterative algorithm to find the error locator polynomial

EVENODD: An Efficient Scheme for Tolerating Double Disk Failures in RAID Architectures

We present a novel method, that we call EVENODD, for tolerating up to two disk failures in RAID architectures. EVENODD employs the addition of only two redundant disks and consists of simple exclusive-OR computations. This redundant storage is optimal, in the sense that two failed disks cannot be retrieved with less than two redundant disks. A major advantage of EVENODD is that it only requires parity hardware, which is typically present in standard RAID-5 controllers. Hence, EVENODD can be implemented on standard RAID-5 controllers without any hardware changes. The most commonly used scheme that employes optimal redundant storage (i.e., two extra disks) is based on Reed-Solomon (RS) error-correcting codes. This scheme requires computation over finite fields and results in a more complex implementation. For example, we show that the complexity of implementing EVENODD in a disk array with 15 disks is about 50% of the one required when using the RS scheme. The new scheme is not limited to RAID architectures: it can be used in any system requiring large symbols and relatively short codes, for instance, in multitrack magnetic recording. To this end, we also present a decoding algorithm for one column (track) in error

Fast decoding of a d(min) = 6 RS code

A method for high speed decoding a d sub min = 6 Reed-Solomon (RS) code is presented. Properties of the two byte error correcting and three byte error detecting RS code are discussed. Decoding using a quadratic equation is shown. Theorems and concomitant proofs are included to substantiate this decoding method

Fast decoding techniques for extended single-and-double-error-correcting Reed Solomon codes

A problem in designing semiconductor memories is to provide some measure of error control without requiring excessive coding overhead or decoding time. For example, some 256K-bit dynamic random access memories are organized as 32K x 8 bit-bytes. Byte-oriented codes such as Reed Solomon (RS) codes provide efficient low overhead error control for such memories. However, the standard iterative algorithm for decoding RS codes is too slow for these applications. Some special high speed decoding techniques for extended single and double error correcting RS codes. These techniques are designed to find the error locations and the error values directly from the syndrome without having to form the error locator polynomial and solve for its roots

A cascaded coding scheme for error control

A cascade coding scheme for error control is investigated. The scheme employs a combination of hard and soft decisions in decoding. Error performance is analyzed. If the inner and outer codes are chosen properly, extremely high reliability can be attained even for a high channel bit-error-rate. Some example schemes are evaluated. They seem to be quite suitable for satellite down-link error control

On Optimal Family of Codes for Archival DNA Storage

DNA based storage systems received attention by many researchers. This includes archival and re-writable random access DNA based storage systems. In this work, we have developed an efficient technique to encode the data into DNA sequence by using non-linear families of ternary codes. In particular, we proposes an algorithm to encode data into DNA with high information storage density and better error correction using a sub code of Golay code. Theoretically, 115 exabytes (EB) data can be stored in one gram of DNA by our method.Comment: Supplementary file and the software DNA Cloud 2.0 is available at http://www.guptalab.org/dnacloud This is the preliminary version of the paper that appeared in Proceedings of IWSDA 2015, pp. 143--14

Techniques for the realization of ultrareliable spaceborne computers Interim scientific report

Error-free ultrareliable spaceborne computer

Coding for reliable satellite communications

This research project was set up to study various kinds of coding techniques for error control in satellite and space communications for NASA Goddard Space Flight Center. During the project period, researchers investigated the following areas: (1) decoding of Reed-Solomon codes in terms of dual basis; (2) concatenated and cascaded error control coding schemes for satellite and space communications; (3) use of hybrid coding schemes (error correction and detection incorporated with retransmission) to improve system reliability and throughput in satellite communications; (4) good codes for simultaneous error correction and error detection, and (5) error control techniques for ring and star networks