Interleaving Gains for Receive Diversity Schemes of Distributed Turbo Codes in Wireless Half–Duplex Relay Channels

This paper proposes the interleaving gain in two different distributed turbo-coding schemes: Distributed Turbo Codes (DTC) and Distributed Multiple Turbo Codes (DMTC) for half-duplex relay system as an extension of our previous work on turbo coding interleaver design for direct communication channel. For these schemes with half-duplex constraint, the source node transmits its information with the parity bit sequence(s) to both the relay and the destination nodes during the first phase. The relay received the data from the source and process it by using decode and forward protocol. For the second transmission period, the decoded systematic data at relay is interleaved and re-encoded by a Recursive Systematic Convolutional (RSC) encoder and forwarded to the destination. At destination node, the signals received from the source and relay are processed by using turbo log-MAP iterative decoding for retrieving the original information bits. We demonstrate via simulations that the interleaving gain has a large effect with DTC scheme when we use only one RSC encoder at both the source and relay with best performance when using Modified Matched S-Random (MMSR) interleaver. Furthermore, by designing a Chaotic Pseudo Random Interleaver (CPRI) as an outer interleaver at the source node instead of classical interleavers, our scheme can add more secure channel conditions

Novel Methods in the Improvement of Turbo Codes and their Decoding

The performance of turbo codes can often be improved by improving the weight spectra of such codes. Methods of producing the weight spectra of turbo codes have been investigated and many improvements were made to refine the techniques. A much faster method of weight spectrum evaluation has been developed that allows calculation of weight spectra within a few minutes on a typical desktop PC. Simulation results show that new high performance turbo codes are produced by the optimisation methods presented. The two further important areas of concern are the code itself and the decoding. Improvements of the code are accomplished through optimisation of the interleaver and choice of constituent coders. Optimisation of interleaves can also be accomplished automatically using the algorithms described in this work. The addition of a CRC as an outer code proved to offer a vast improvement on the overall code performance. This was achieved without any code rate loss as the turbo code is punctured to make way for the CRC remainder. The results show a gain of 0.4dB compared to the non-CRC (1014,676) turbo code. Another improvement to the decoding performance was achieved through a combination of MAP decoding and Ordered Reliability decoding. The simulations show a performance of just 0.2dB from the Shannon limit. The same code without ordered reliability decoding has a performance curve which is 0.6dB from the Shannon limit. In situations where the MAP decoder fails to converge ordered reliability decoding succeeds in producing a codeword much closer to the received vector, often the correct codeword. The ordered reliability decoding adds to the computational complexity but lends itself to FPGA implementation.Engineering and Physical Sciences Research Council (EPSRC