Test Strategies for Low Power Devices

Ultra low-power devices are being developed for embedded applications in bio-medical electronics, wireless sensor networks, environment monitoring and protection, etc. The testing of these low-cost, low-power devices is a daunting task. Depending on the target application, there are stringent guidelines on the number of defective parts per million shipped devices. At the same time, since such devices are cost-sensitive, test cost is a major consideration. Since system-level power-management techniques are employed in these devices, test generation must be power-management-aware to avoid stressing the power distribution infrastructure in the test mode. Structural test techniques such as scan test, with or without compression, can result in excessive heat dissipation during testing and damage the package. False failures may result due to the electrical and thermal stressing of the device in the test mode of operation, leading to yield loss. This paper considers different aspects of testing low-power devices and some new techniques to address these problems.Design, Automation and Test in Europe (DATE \u2708), 10-14 March 2008, Munich, German

UML-Based co-design framework for body sensor network applications

Ph.DDOCTOR OF PHILOSOPH

MINING SECURE BEHAVIOR OF HARDWARE DESIGNS

Hardware presents an enticing target for attackers attempting to gain access to a secured com-puter system. Software-only exploits of hardware vulnerabilities may bypass software level secu-rity features. Hardware must be made secure. However, to understand whether a hardware designis secure, security specifications must be generated to define security on that design. Micro-architectural design elements, undocumented or under-documented features, debug interfaces,and information–flow side channels all may introduce new vulnerabilities. The secure behaviorof each must be specified in order ensure the design meets its security requirements and containsno vulnerabilities. However, manual efforts can be overwhelmed by design complexity, and manyhardware vulnerabilities, such as Memory Sinkhole, SYSRET privilege escalation, and mostrecently Spectre/Meltdown, persisted in product lines for decades despite extensive testing. Anautomated solution is needed to specify secure designs.Specification mining offers a solution by automating security specification for hardware.Specification miners use a form of machine learning to specify behaviors of a system by studyinga system in execution. However, specification mining was first developed for use with software.Complex hardware designs offer unique challenges for this technique. Further, specificationminers traditionally capture functional specifications without a notion of security, and may notuse the specification logics necessary to describe some security requirements.This work demonstrates specification mining for hardware security. On CISC architecturessuch as x86, I demonstrate that a miner partitioning the design state space along control signalsdiscovers a specification that includes manually defined properties and, if followed, would secureCPU designs against Memory Sinkhole and SYSRET privilege escalation. For temporal prop-erties, I demonstrate that a miner using security specific linear temporal logic (LTL) templatesfor specification detection may find properties that, if followed, would secure designs againsthistorical documented security vulnerabilities and against potential future attacks targeting sys-tem initialization. For information–flow hyperproperties, I demonstrate that a miner may useInformation Flow Tracking (IFT) to develop output properties containing designer specifiedinformation–flow security properties as well as properties that demonstrate a design does notcontain certain Common Weakness Enumerations (CWEs).Doctor of Philosoph