Development Of Inductively-Degenerated LNA For W-CDMA Application Utilizing 0.18 Um RFCMOS Technology

Satu metodologi terperinci dan bersistematik untuk merekabentuk penguat hingar rendah (LNA) induktif ternyahjana kaskod, juga dikenali sebagai topologi Padanan Masukan dan Hingar Serentak (SNIM), A detailed and systematic methodology on the design of the inductivelydegenerated cascode LNA, also known as the Simultaneously Noise and Input Matching (SNIM) LNA

Integrated phased array systems in silicon

Silicon offers a new set of possibilities and challenges for RF, microwave, and millimeter-wave applications. While the high cutoff frequencies of the SiGe heterojunction bipolar transistors and the ever-shrinking feature sizes of MOSFETs hold a lot of promise, new design techniques need to be devised to deal with the realities of these technologies, such as low breakdown voltages, lossy substrates, low-Q passives, long interconnect parasitics, and high-frequency coupling issues. As an example of complete system integration in silicon, this paper presents the first fully integrated 24-GHz eight-element phased array receiver in 0.18-μm silicon-germanium and the first fully integrated 24-GHz four-element phased array transmitter with integrated power amplifiers in 0.18-μm CMOS. The transmitter and receiver are capable of beam forming and can be used for communication, ranging, positioning, and sensing applications

Low-noise amplifiers for integrated multi-mode direct-conversion receivers

The evolution of wireless telecommunication systems during the last decade has been rapid. During this time the design driver has shifted towards fast data applications instead of speech. In addition, the different systems may have a limited coverage, for example, limited to urban areas only. Thus, it has become important for a mobile terminal to be able to use different wireless systems, depending on the application chosen and the location of the terminal. The choice of receiver architecture affects the performance, size, and cost of the receiver. The superheterodyne receiver has hitherto been the dominant radio architecture, because of its good sensitivity and selectivity. However, superheterodyne receivers require expensive filters, which, with the existing technologies, cannot be integrated on the same chip as the receiver. Therefore, architectures using a minimum number of external components, such as direct conversion, have become popular. In addition, compared to the superheterodyne architecture, the direct-conversion architecture has benefits when multi-mode receivers, which are described in this thesis, are being designed. In this thesis, the limitations placed on the analog receiver by different system specifications are introduced. The estimations for the LNA specifications are derived from these specifications. In addition, the limitations imposed by different types of receiver architectures are described. The inductively-degenerated LNA is the basis for all the experimental circuits. The different components for this configuration are analyzed and compared to other commonly-used configurations in order to justify the use of an inductively-degenerated LNA. Furthermore, the design issues concerning the LNA-mixer interface in direct-conversion receivers are analyzed. Without knowing these limitations, it becomes difficult to understand the choices made in the experimental circuits. One of the key parts of this thesis describes the design and implementation of a single-chip multi-mode LNA, which is one of the key blocks in multi-mode receivers. The multi-mode structures in this thesis were developed for a direct-conversion receiver where only one system is activated at a time. The LNA interfaces to a pre-select filter and mixers and the different LNA components are analyzed in detail. Furthermore, the design issues related to possible interference from additional systems on single-chip receivers are analyzed and demonstrated. A typical receiver includes variable gain, which can be implemented both in the analog baseband and/or in the RF. If the variable gain is implemented in the RF parts, it is typically placed in the LNA or in a separate gain control stage. Several methods that can be used to implement a variable gain in the LNA are introduced and compared to each other. Furthermore, several of these methods are included in the experimental circuits. The last part of this thesis concentrates on four experimental circuits, which are described in this thesis. The first two chips describe an RF front-end and a direct-conversion receiver for WCDMA applications. The whole receiver demonstrates that it is possible to implement A/D converters on the same chip as sensitive RF blocks without significantly degrading receiver performance. The other two chips describe an RF front-end for WCDMA and GSM900 applications and a direct-conversion receiver for GSM900, DCS1800, PCS1900 and WCDMA systems. These ICs demonstrate the usability of the circuit structure developed and presented in this thesis. The chip area in the last multi-mode receiver is not significantly increased compared to corresponding single-system receivers.reviewe

Design of an adaptive LNA for hand-held devices in a 1-V 90-nm standard RF CMOS technology: From circuit analysis to layout

This paper deals the design of a reconfigurable Low-Noise Amplifier (LNA) for the next generation of wireless hand-held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand-work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two-stage topology including inductive-source degeneration, MOS-varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b-g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF16dB, S11-3.3 dBm over the 1.85-2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1-V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.Este trabajo presenta el diseño de un amplificador de bajo ruido, LNA (del inglés Low‐Noise Amplifier) reconfigurable para la siguiente generación de dispositivos portátiles de comunicación inalámbricos, usando la aproximación de circuitos concentrados sustentada en leyes físicas. El propósito de este trabajo no es sólo presentar resultados de simulación que muestran el cumplimiento de especificaciones para cada estándar, sino también demostrar que cada paso de diseño tiene un significado físico haciendo que el procedimiento matemático de diseño sea simple y adecuado para el trabajo a mano tanto para actividades en laboratorio como en el aula. El circuito bajo análisis, diseñado en una tecnología CMOS 90nm, consta de dos etapas que incluyen degeneración inductiva de fuente, redes de entonado basadas en varactores MOS, y corrientes de polarización programables. Esta propuesta, con reducido número de inductores y mínima disipación de potencia, adapta su desempeño a las diversas especificaciones de cada estándar; el LNA se diseña para cubrir los requerimientos de GSM (PCS1900), WCDMA, Bluetooth y WLAN (IEEE 802.11b‐g). Para evaluar el efecto de las no idealidades de la tecnología en el desempeño del LNA, las simulaciones demuestran que el circuito cumple parámetros como NF16dB, S11‐3.3dBm en la banda 1.85‐ 2.48GHz. Para todos los estándares bajo estudio, el consumo adaptivo de potencia varía de 25.3 mW a 53.3mW usando una fuente de alimentación de 1‐V. El patrón geométrico del LNA reconfigurable consume un área de 1.8mm2

Design of an adaptive LNA for hand-held devices in a 1-V 90-nm standard RF CMOS technology: From circuit analysis to layout

[EN]: This paper deals the design of a reconfigurable Low-Noise Amplifier (LNA) for the next generation of wireless hand-held devices by using a lumped circuit approach based on physical laws. The purpose is not only to present simulation results showing the fulfillment of different standard specifications, but also to demonstrate that each design step has a physical meaning such that the mathematical design flow is simple as well as suitable for hand-work in both laboratory and classroom. The circuit under analysis, which is designed according to technological design rules of a 90nm CMOS technology, is a two-stage topology including inductive-source degeneration, MOS-varactor based tuning networks, and programmable bias currents. This proposal, with reduced number of inductors and minimum power dissipation, adapts its performance to different standard specifications; the LNA is designed to cope with the requirements of GSM (PCS1900), WCDMA, Bluetooth and WLAN (IEEE 802.11b-g). In order to evaluate the effect of technology parasitics on the LNA performance, simulation results demonstrate that the LNA features NF16dB, S11-3.3 dBm over the 1.85-2.48 GHz band. For all the standards under study the adaptive power consumption varies from 25.3 mW to 53.3mW at a power supply of 1-V. The layout of the reconfigurable LNA occupies an area of 1.8mm2.[ES]: Este trabajo presenta el diseño de un amplificador de bajo ruido, LNA (del inglés Low‐Noise Amplifier) reconfigurable para la siguiente generación de dispositivos portátiles de comunicación inalámbricos, usando la aproximación de circuitos concentrados sustentada en leyes físicas. El propósito de este trabajo no es sólo presentar resultados de simulación que muestran el cumplimiento de especificaciones para cada estándar, sino también demostrar que cada paso de diseño tiene un significado físico haciendo que el procedimiento matemático de diseño sea simple y adecuado para el trabajo a mano tanto para actividades en laboratorio como en el aula. El circuito bajo análisis, diseñado en una tecnología CMOS 90nm, consta de dos etapas que incluyen degeneración inductiva de fuente, redes de entonado basadas en varactores MOS, y corrientes de polarización programables. Esta propuesta, con reducido número de inductores y mínima disipación de potencia, adapta su desempeño a las diversas especificaciones de cada estándar; el LNA se diseña para cubrir los requerimientos de GSM (PCS1900), WCDMA, Bluetooth y WLAN (IEEE 802.11b‐g). Para evaluar el efecto de las no idealidades de la tecnología en el desempeño del LNA, las simulaciones demuestran que el circuito cumple parámetros como NF16dB, S11< ‐5.5dB, S22‐3.3dBm en la banda 1.85‐ 2.48GHz. Para todos los estándares bajo estudio, el consumo adaptivo de potencia varía de 25.3 mW a 53.3mW usando una fuente de alimentación de 1‐V. El patrón geométrico del LNA reconfigurable consume un área de 1.8mm2.Peer Reviewe

A Fully Integrated 24-GHz Eight-Element Phased-Array Receiver in Silicon

This paper reports the first fully integrated 24-GHz eight-element phased-array receiver in a SiGe BiCMOS technology. The receiver utilizes a heterodyne topology and the signal combining is performed at an IF of 4.8 GHz. The phase-shifting with 4 bits of resolution is realized at the LO port of the first down-conversion mixer. A ring LC voltage-controlled oscillator (VCO) generates 16 different phases of the LO. An integrated 19.2-GHz frequency synthesizer locks the VCO frequency to a 75-MHz external reference. Each signal path achieves a gain of 43 dB, a noise figure of 7.4 dB, and an IIP3 of -11 dBm. The eight-path array achieves an array gain of 61 dB and a peak-to-null ratio of 20 dB and improves the signal-to-noise ratio at the output by 9 dB

A Multiband Low Noise Amplifier for Software Defined Radio Using Switchable Active Shunt Feedback Input Matching

Radio frequency (RF) receivers are the key front-end blocks in wireless devices such as smartphones, pagers, PDAs etc. An important block of the RF receiver is the Low-noise amplifier. It’s function is to amplify with little noise addition, the RF signal received at the atenna. Modern wireless devices for example the smartphone, incorporates multiple functionalities supported by various RF standards- GPS, Bluetooth, Wifi, GSM etc. Thus, the current trend in the wireless technology is to integrate radio receivers for each RF standard into a single system-on-chip (SoC) in order to reduce cost and area of the devices. In view of this, multiband RF receivers have been developed which feature multiband LNAs. This thesis presents the design and implementation of a multiband LNA for Software Defined Radio Applications. In this thesis, basic radio-frequency concepts are discussed which is followed by a discussion of pros and cons of various multistandard low-noise amplifier topologies. This is then followed by the design of the proposed reconfigurable LNA. The LNA is designed and fabricated in IBM 0.18um CMOS technology. It is made up of dual LC resonant tanks, one to switch between 5.2GHz and 3.5GHz frequency bands and the other, to switch between 2.4GHz and 1.8GHz bands. The input matching of the LNA is achieved using a switchable shunt active feedback network. The LNA achieves S21 of between 10.1dB and 13.43dB. It achieves an input matching (S11) between -13.44 dB and -11.97 dB. The noise figure measured ranges from 2.8 dB to 4.3 dB. The LNA also achieves an IIP3 from -7.12 dBm to -3.45 dBm at 50 MHz offset. The power consumption ranges from 7 mW to 7.2 mW

Design Concepts of Low-Noise Amplifier for Radio Frequency Receivers

The development of high-performance radio frequency (RF) transceivers or multi-standard/reconfigurable receivers requires an innovative RF front-end design to ensure the best from a good technology. In general, the performance of front-end and/or building blocks can be improved only by an increase in the supply voltage, width of the transistors or an additional stage at the output of a circuit. This leads to increase the design issues like circuit size and the power consumption. Presently, the wireless market and the need to develop efficient portable electronic systems have pushed the industry to the production of circuit designs with low-voltage power supply. The objective of this work is to introduce an innovative single-stage design structure of low noise amplifier (LNA) to achieve higher performance under low operating voltage. TSMC 0.18 micron CMOS technology scale is utilized for realizing LNA designs and the simulation process is carried out with a supply voltage of 1.8 V. The LNA performance measures are analyzed by using an Intel Core2 duo CPU [email protected] processor with Agilent’s Advanced Design System (ADS) 2009 version software