Active Pixel Sensor Architectures for High Resolution Large Area Digital Imaging

This work extends the technology of amorphous silicon (a-Si) thin film transistors (TFTs) from traditional switching applications to on-pixel signal amplification for large area digital imaging and in particular, is aimed towards enabling emerging low noise, high resolution and high frame rate medical diagnostic imaging modalities such as digital tomosynthesis. A two transistor (2T) pixel amplifier circuit based on a novel charge-gate thin film transistor (TFT) device architecture is introduced to shrink the TFT based pixel readout circuit size and complexity and thus, improve the imaging array resolution and reliability of the TFT fabrication process. The high resolution pixel amplifier results in improved electrical performance such as on-pixel amplification gain, input referred noise and faster readouts. In this research, a charge-gated TFT that operates as both a switched amplifier and driver is used to replace two transistors (the addressing switch and the amplifier transistor) of previously reported three transistor (3T) APS pixel circuits.. In addition to enabling smaller pixels, the proposed 2T pixel amplifier results in better signal-to-noise (SNR) by removing the large flicker noise source associated with the switched TFT and increased pixel transconductance gain since the large ON-state resistance of the switched TFT is removed from the source of the amplifier TFT. Alternate configurations of 2T APS architectures based on source or drain switched TFTs are also investigated, compared, and contrasted to the gate switched architecture using charge-gated TFT. A new driving scheme based on multiple row resetting is introduced which combined with the on-pixel gain of the APS, offers considerable improvements in imaging frame rates beyond those feasible for PPS based pixels. The novel developed 2T APS architectures is implemented in single pixel test structures and in 88 pixel test arrays with a pixel pitch of 100 µm. The devices were fabricated using an in-house developed top-gate TFT fabrication process. Measured characteristics of the test devices confirm the performance expectations of the 2T architecture design. Based on parameters extracted from fabricated TFTs, the input referred noise is calculated, and the instability in pixel transconductance gain over prolonged operation tine is projected for different imaging frame rates. 2T APS test arrays were packaged and integrated with an amorphous selenium (a-Se) direct x-ray detector, and the x-ray response of the a-Se detector integrated with the novel readout circuit was evaluated. The special features of the APS such as non-destructive readout and voltage programmable on-pixel gain control are verified. The research presented in this thesis extends amorphous silicon pixel amplifier technology into the area of high density pixel arrays such as large area medical X-ray imagers for digital mammography tomosynthesis. It underscores novel device and circuit design as an effective method of overcoming the inherent shortcomings of the a-Si material . Although the developed device and circuit ideas were implemented and tested using a-Si TFTs, the scope of the device and circuit designs is not limited to amorphous silicon technology and has the potential to be applied to more mainstream technologies, for example, in CMOS active pixel sensor (APS) based digital cameras

Ternary Logic Design in Topological Quantum Computing

A quantum computer can perform exponentially faster than its classical counterpart. It works on the principle of superposition. But due to the decoherence effect, the superposition of a quantum state gets destroyed by the interaction with the environment. It is a real challenge to completely isolate a quantum system to make it free of decoherence. This problem can be circumvented by the use of topological quantum phases of matter. These phases have quasiparticles excitations called anyons. The anyons are charge-flux composites and show exotic fractional statistics. When the order of exchange matters, then the anyons are called non-Abelian anyons. Majorana fermions in topological superconductors and quasiparticles in some quantum Hall states are non-Abelian anyons. Such topological phases of matter have a ground state degeneracy. The fusion of two or more non-Abelian anyons can result in a superposition of several anyons. The topological quantum gates are implemented by braiding and fusion of the non-Abelian anyons. The fault-tolerance is achieved through the topological degrees of freedom of anyons. Such degrees of freedom are non-local, hence inaccessible to the local perturbations. In this paper, the Hilbert space for a topological qubit is discussed. The Ising and Fibonacci anyonic models for binary gates are briefly given. Ternary logic gates are more compact than their binary counterparts and naturally arise in a type of anyonic model called the metaplectic anyons. The mathematical model, for the fusion and braiding matrices of metaplectic anyons, is the quantum deformation of the recoupling theory. We proposed that the existing quantum ternary arithmetic gates can be realized by braiding and topological charge measurement of the metaplectic anyons

Electronic paper in color by electrochromic materials and plasmonics

The most common display today is emissive. It produces its own light and emits it to the viewer\u27s eye. A reflective display, also known as electronic paper, uses ambient light and reflects it to the viewer, just like a newspaper. Electronic paper has some advantages over emissive displays such as: lower power consumption and readability in sunlight. Today, electronic papers in color lack a desirable color gamut - the colors look bad. The purpose of this thesis is to investigate how structural colors, plasmonics and electrochromics can be used to increase the optical performance of electronic paper in color.By using structural colors (metal-insulator-metal) and plasmonics, we could create highly reflective color pixels. The pixels could be made to turn ON and OFF using electrochromic materials. In this thesis, conjugated polymers (PProDOT-Me2 and PProDOP) or tungsten oxide were employed. The reflection difference between the ON and OFF states was 60%. This was better than previously reported values for other electrochromic materials.If the electrochromic material instead was incorporated into the nanostructure (metal-electrochromics-metal), applying a voltage would then alter the color of the pixel. If tungsten oxide was used inside the structure, the color of one pixel could change, but it would not be able to span the whole visible spectra. If, instead, the conjugated polymer (PT34bT) was used inside the structure, the whole visible spectra could be accessed with one pixel.To create a real display, it is not enough to have one pixel that can change color. Millions of pixels in a grid are necessary. This poses a problem since each pixel needs to be individually contacted. This can be overcome by using a matrix configuration such as a passive matrix (PM) or an active matrix (AM). This thesis investigates both these configurations. PM requires the color change to be strongly non-linear with the applied voltage. It must have memory such as hysteresis. This effect can be incorporated by utilizing an indium-tin-oxide electrode as a counter electrode to a metal working electrode coated with a conjugated polymer as electrochromic material. To avoid crosstalk between pixels, a photo patterned electrolyte was used.Commercial thin-film transistor arrays were used for AM configuration. The red, green, and blue nanostructures were deposited on the array. The conjugated polymer PProDOT-Me2 is synthesized directly on individual pixels and switched without crosstalk

SCEE 2008 book of abstracts : the 7th International Conference on Scientific Computing in Electrical Engineering (SCEE 2008), September 28 – October 3, 2008, Helsinki University of Technology, Espoo, Finland

This report contains abstracts of presentations given at the SCEE 2008 conference.reviewe

Integrated Circuits/Microchips

With the world marching inexorably towards the fourth industrial revolution (IR 4.0), one is now embracing lives with artificial intelligence (AI), the Internet of Things (IoTs), virtual reality (VR) and 5G technology. Wherever we are, whatever we are doing, there are electronic devices that we rely indispensably on. While some of these technologies, such as those fueled with smart, autonomous systems, are seemingly precocious; others have existed for quite a while. These devices range from simple home appliances, entertainment media to complex aeronautical instruments. Clearly, the daily lives of mankind today are interwoven seamlessly with electronics. Surprising as it may seem, the cornerstone that empowers these electronic devices is nothing more than a mere diminutive semiconductor cube block. More colloquially referred to as the Very-Large-Scale-Integration (VLSI) chip or an integrated circuit (IC) chip or simply a microchip, this semiconductor cube block, approximately the size of a grain of rice, is composed of millions to billions of transistors. The transistors are interconnected in such a way that allows electrical circuitries for certain applications to be realized. Some of these chips serve specific permanent applications and are known as Application Specific Integrated Circuits (ASICS); while, others are computing processors which could be programmed for diverse applications. The computer processor, together with its supporting hardware and user interfaces, is known as an embedded system.In this book, a variety of topics related to microchips are extensively illustrated. The topics encompass the physics of the microchip device, as well as its design methods and applications

Design of Neuromemristive Systems for Visual Information Processing

Neuromemristive systems (NMSs) are brain-inspired, adaptive computer architectures based on emerging resistive memory technology (memristors). NMSs adopt a mixed-signal design approach with closely-coupled memory and processing, resulting in high area and energy efficiencies. Previous work suggests that NMSs could even supplant conventional architectures in niche application domains such as visual information processing. However, given the infancy of the field, there are still several obstacles impeding the transition of these systems from theory to practice. This dissertation advances the state of NMS research by addressing open design problems spanning circuit, architecture, and system levels. Novel synapse, neuron, and plasticity circuits are designed to reduce NMSs’ area and power consumption by using current-mode design techniques and exploiting device variability. Circuits are designed in a 45 nm CMOS process with memristor models based on multilevel (W/Ag-chalcogenide/W) and bistable (Ag/GeS2/W) device data. Higher-level behavioral, power, area, and variability models are ported into MATLAB to accelerate the overall simulation time. The circuits designed in this work are integrated into neural network architectures for visual information processing tasks, including feature detection, clustering, and classification. Networks in the NMSs are trained with novel stochastic learning algorithms that achieve 3.5 reduction in circuit area, reduced design complexity, and exhibit similar convergence properties compared to the least-mean-squares algorithm. This work also examines the effects of device-level variations on NMS performance, which has received limited attention in previous work. The impact of device variations is reduced with a partial on-chip training methodology that enables NMSs to be configured with relatively sophisticated algorithms (e.g. resilient backpropagation), while maximizing their area-accuracy tradeoff

Multi-mode Pixel Architectures for Large Area Real-Time X-ray Imaging

The goal of this work is to extend the state-of-the-art in digital medical X-ray imaging as it pertains to real-time, low-noise imaging and multi-mode imager functionality. One focus of this research in digital flat-panel imagers is to increase the detective quantum efficiency, particularly at low X-ray exposures, in order to enable low-noise imaging applications such as fluoroscopy or tomographic mammography. Another focus of this research is in the creation of a multi-mode imager, such as a combined radiographic and fluoroscopic (R&F) imager, which will reduce hospital costs, both in terms of equipment acquisition and storage space. To that end, we propose a novel three-transistor multi-mode digital flat-panel imager with a dynamic range capable for use in R&F applications, with a particular focus on noise optimization for low-noise real-time digital flat-panel X-ray fluoroscopy. This work involves the derivation and optimization of the total input referred noise of an active pixel sensor (APS) in terms of the on-pixel thin-film transistor device dimensions. It is determined that in order to minimize noise, all non-transistor capacitances at the pixel sense node needed to be minimized. This leads to a design where the on-pixel storage capacitance is eliminated; and instead the gate capacitance of the sense-node transistor is used to store the incoming X-ray converted charge. This work allows researchers to gain insight into the fundamental noise operation of active pixels used in medical imaging, and to appropriately choose device dimensions. Due to the inherent large feature sizes of thin-film transistors, active pixel flat-panel X-ray medical imagers offer lower resolution than their film-screen counterparts. By demonstrating the desirability of smaller device dimensions for reduced noise and the elimination of a storage capacitor, this research frees some of the area constraints that exist in active pixel flat-panel imagers, allowing for smaller pixels, and thus higher resolution medical imagers. The noise analysis and optimization as a function of pixel TFT device dimensions in this work is applicable to any amorphous silicon (a-Si) based charge-sensitive pixel, and is easily extended to other device technologies such as polysilicon (poly-Si). iv In addition, experimental results of a 64x64 pixel four-transistor APS imaging array fabricated in a-Si technology and mated with an a-Se photoconductor for use in medical X-ray imaging is presented. MTF results and transient response in the presence of X-rays (image lag) for the APS array are poor, which is ascribed to high charge trapping at the silicon nitride/a-Se interface. Improvements to the silicon nitride passivation layer and pixel layout are suggested to reduce this charge trapping. The prototype imager is compared directly with a state-of-the-art a-Si PPS imaging array and demonstrates good SNR performance for X-ray exposures down to 1.5μR. Pixel design and fabrication process improvements are suggested for low-exposure APS testing and improved low-noise performance