Analisi degli effetti di guasti transitori di memorie resistive

L'elaborato di tesi, argomenta il problema degli errori transitori nell'array di memoria ReRAM, in cui i driver sono colpiti da particelle energetiche. Viene messo in evidenza l'aumento di suscettibilità a questi errori, proporzionale all'aging dei driver. Sono mostrate simulazioni, in cui sono quantificati gli upset avvenuti nelle celle di memoria

DESIGN AND TEST OF DIGITAL CIRCUITS AND SYSTEMS USING CMOS AND EMERGING RESISTIVE DEVICES

The memristor is an emerging nano-device. Low power operation, high density, scalability, non-volatility, and compatibility with CMOS Technology have made it a promising technology for memory, Boolean implementation, computing, and logic systems. This dissertation focuses on testing and design of such applications. In particular, we investigate on testing of memristor-based memories, design of memristive implementation of Boolean functions, and reliability and design of neuromorphic computing such as neural network. In addition, we show how to modify threshold logic gates to implement more functions. Although memristor is a promising emerging technology but is prone to defects due to uncertainties in nanoscale fabrication. Fast March tests are proposed in Chapter 2 that benefit from fast write operations. The test application time is reduced significantly while simultaneously reducing the average test energy per cell. Experimental evaluation in 45 nm technology show a speed-up of approximately 70% with a decrease in energy by approximately 40%. DfT schemes are proposed to implement the new test methods. In Chapter 3, an Integer Linear Programming based framework to identify current-mode threshold logic functions is presented. It is shown that threshold logic functions can be implemented in CMOS-based current mode logic with reduced transistor count when the input weights are not restricted to be integers. Experimental results show that many more functions can be implemented with predetermined hardware overhead, and the hardware requirement of a large percentage of existing threshold functions is reduced when comparing to the traditional CMOS-based threshold logic implementation. In Chapter 4, a new method to implement threshold logic functions using memristors is presented. This method benefits from the high range of memristor’s resistivity which is used to define different weight values, and reduces significantly the transistor count. The proposed approach implements many more functions as threshold logic gates when comparing to existing implementations. Experimental results in 45 nm technology show that the proposed memristive approach implements threshold logic gates with less area and power consumption. Finally, Chapter 5 focuses on current-based designs for neural networks. CMOS aging impacts the total synaptic current and this impacts the accuracy. Chapter 5 introduces an enhanced memristive crossbar array (MCA) based analog neural network architecture to improve reliability due to the aging effect. A built-in current-based calibration circuit is introduced to restore the total synaptic current. The calibration circuit is a current sensor that receives the ideal reference current for non-aged column and restores the reduced sensed current at each column to the ideal value. Experimental results show that the proposed approach restores the currents with less than 1% precision, and the area overhead is negligible

Towards Data Reliable, Low-Power, and Repairable Resistive Random Access Memories

A series of breakthroughs in memristive devices have demonstrated the potential of memristor arrays to serve as next generation resistive random access memories (ReRAM), which are fast, low-power, ultra-dense, and non-volatile. However, memristors' unique device characteristics also make them prone to several sources of error. Owing to the stochastic filamentary nature of memristive devices, various recoverable errors can affect the data reliability of a ReRAM. Permanent device failures further limit the lifetime of a ReRAM. This dissertation developed low-power solutions for more reliable and longer-enduring ReRAM systems. In this thesis, we first look into a data reliability issue known as write disturbance. Writing into a memristor in a crossbar could disturb the stored values in other memristors that are on the same memory line as the target cell. Such disturbance is accumulative over time which may lead to complete data corruption. To address this problem, we propose the use of two regular memristors on each word to keep track of the disturbance accumulation and trigger a refresh to restore the weakened data, once it becomes necessary. We also investigate the considerable variation in the write-time characteristics of individual memristors. With such variation, conventional fixed-pulse write schemes not only waste significant energy, but also cannot guarantee reliable completion of the write operations. We address such variation by proposing an adaptive write scheme that adjusts the width of the write pulses for each memristor. Our scheme embeds an online monitor to detect the completion of a write operation and takes into account the parasitic effect of line-shared devices in access-transistor-free memristive arrays. We further investigate the use of this method to shorten the test time of memory march algorithms by eliminating the need of a verifying read right after a write, which is commonly employed in the test sequences of march algorithms.Finally, we propose a novel mechanism to extend the lifetime of a ReRAM by protecting it against hard errors through the exploitation of a unique feature of bipolar memristive devices. Our solution proposes an unorthodox use of complementary resistive switches (a particular implementation of memristive devices) to provide an ``in-place spare'' for each memory cell at negligible extra cost. The in-place spares are then utilized by a repair scheme to repair memristive devices that have failed at a stuck-at-ON state at a page-level granularity. Furthermore, we explore the use of in-place spares in lieu of other memory reliability and yield enhancement solutions, such as error correction codes (ECC) and spare rows. We demonstrate that with the in-place spares, we can yield the same lifetime as a baseline ReRAM with either significantly fewer spare rows or a lighter-weight ECC, both of which can save on energy consumption and area

On Defect Oriented Testing for Hybrid CMOS/memristor Memory

Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliability improvement. However, research on defect analysis for yield and quality improvement is still in its infancy stage. This paper presents a framework of defect oriented testing in hybrid memory based on electrical simulation. First, a classification and definition of defects is introduced. Second, a simulation model for defect injection and circuit simulation is proposed. Third, a case study to illustrate how the proposed approach can be used to analyze the defects and translate their electrical faulty behavior into fault models - in order to develop the appropriate tests and design for testability schemes - is provided. The simulation results show that in addition to the occurrence of conventional semiconductor memories faults, new unique faults take place, e.g., faults that cause the cell to hold an undefined state. These new unique faults require new test approaches (e.g., DfT) in order to be able to detect them

On Defect Oriented Testing for Hybrid CMOS/memristor Memory

Hybrid CMOS/memristor memory (hybrid memory) technology is one of the emerging memory technologies potentially to replace conventional non-volatile flash memory. Existing research on such novel circuits focuses mainly on the integration between CMOS and non-CMOS, fabrication techniques and reliability improvement. However, research on defect analysis for yield and quality improvement is still in its infancy stage. This paper presents a framework of defect oriented testing in hybrid memory based on electrical simulation. First, a classification and definition of defects is introduced. Second, a simulation model for defect injection and circuit simulation is proposed. Third, a case study to illustrate how the proposed approach can be used to analyze the defects and translate their electrical faulty behavior into fault models - in order to develop the appropriate tests and design for testability schemes - is provided. The simulation results show that in addition to the occurrence of conventional semiconductor memories faults, new unique faults take place, e.g., faults that cause the cell to hold an undefined state. These new unique faults require new test approaches (e.g., DfT) in order to be able to detect them