Speeding Up Technology-Independent Timing Optimization by Network Partitioning

Abstract Technology-independenttiming optimizationis an importantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite slow and thus impractical for large networks. In this paper, we propose DE-PART, a delay-basedpartitioner-cum-optimizer, which purports to solve this problem. Given a combinational logic network that is to be optimized for timing, DEPART divides it into sub-networks using timing information and a constraint on the maximum number of gates allowed in a single sub-network. These sub-networks are then dispatched, one by one, to a standard timing optimizer. The optimized sub-networks are re-glued, generating an optimized network. The challenge is how to partition the original network into sub-networks so that the nal solution quality after partitioning and optimization is comparable to that from the timing optimizer. We propose a partitioning technique that is timing-driven and is simple yet e ective. We compare DEPART with speed up 21 , a state-of-the-art timing optimization tool, and with various partitioning techniques such as min-cut based and region growing, on a suite of large industrial and ISCAS circuits. On more than half of the benchmarks, DEPART yields run-time improvements of 20 to 450 times over a normal invocation of speed up the overall average improvement being 8 times, without compromising the solution quality m uch. Min-cut and region growing partitioning schemes, not being timing-driven, perform poorly in terms of the nal circuit delay

Delay driven multi-way circuit partitioning.

Wong Sze Hon.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 88-91).Abstracts in English and Chinese.Chapter 1 --- Introduction --- p.1Chapter 1.1 --- Preliminaries --- p.1Chapter 1.2 --- Motivations --- p.1Chapter 1.3 --- Contributions --- p.3Chapter 1.4 --- Organization of the Thesis --- p.4Chapter 2 --- VLSI Physical Design Automation --- p.5Chapter 2.1 --- Preliminaries --- p.5Chapter 2.2 --- VLSI Design Cycle [1] --- p.6Chapter 2.2.1 --- System Specification --- p.6Chapter 2.2.2 --- Architectural Design --- p.6Chapter 2.2.3 --- Functional Design --- p.6Chapter 2.2.4 --- Logic Design --- p.8Chapter 2.2.5 --- Circuit Design --- p.8Chapter 2.2.6 --- Physical Design --- p.8Chapter 2.2.7 --- Fabrication --- p.8Chapter 2.2.8 --- Packaging and Testing --- p.9Chapter 2.3 --- Physical Design Cycle [1] --- p.9Chapter 2.3.1 --- Partitioning --- p.9Chapter 2.3.2 --- Floorplanning and Placement --- p.11Chapter 2.3.3 --- Routing --- p.11Chapter 2.3.4 --- Compaction --- p.12Chapter 2.3.5 --- Extraction and Verification --- p.12Chapter 2.4 --- Chapter Summary --- p.12Chapter 3 --- Recent Approaches on Circuit Partitioning --- p.14Chapter 3.1 --- Preliminaries --- p.14Chapter 3.2 --- Circuit Representation --- p.15Chapter 3.3 --- Delay Modelling --- p.16Chapter 3.4 --- Partitioning Objectives --- p.19Chapter 3.4.1 --- Interconnections between Partitions --- p.19Chapter 3.4.2 --- Delay Minimization --- p.19Chapter 3.4.3 --- Area and Number of Partitions --- p.20Chapter 3.5 --- Partitioning Algorithms --- p.20Chapter 3.5.1 --- Cut-size Driven Partitioning Algorithm --- p.21Chapter 3.5.2 --- Delay Driven Partitioning Algorithm --- p.32Chapter 3.5.3 --- Acyclic Circuit Partitioning Algorithm --- p.33Chapter 4 --- Clustering Based Acyclic Multi-way Partitioning --- p.38Chapter 4.1 --- Preliminaries --- p.38Chapter 4.2 --- Previous Works on Clustering Based Partitioning --- p.39Chapter 4.2.1 --- Multilevel Circuit Partitioning [2] --- p.40Chapter 4.2.2 --- Cluster-Oriented Iterative-Improvement Partitioner [3] --- p.42Chapter 4.2.3 --- Section Summary --- p.44Chapter 4.3 --- Problem Formulation --- p.45Chapter 4.4 --- Clustering Based Acyclic Multi-Way Partitioning --- p.46Chapter 4.5 --- Modified Fan-out Free Cone Decomposition --- p.47Chapter 4.6 --- Clustering Phase --- p.48Chapter 4.7 --- Partitioning Phase --- p.51Chapter 4.8 --- The Acyclic Constraint --- p.52Chapter 4.9 --- Experimental Results --- p.57Chapter 4.10 --- Chapter Summary --- p.58Chapter 5 --- Network Flow Based Multi-way Partitioning --- p.61Chapter 5.1 --- Preliminaries --- p.61Chapter 5.2 --- Notations and Definitions --- p.62Chapter 5.3 --- Net Modelling --- p.63Chapter 5.4 --- Previous Works on Network Flow Based Partitioning --- p.64Chapter 5.4.1 --- Network Flow Based Min-Cut Balanced Partitioning [4] --- p.65Chapter 5.4.2 --- Network Flow Based Circuit Partitioning for Time-multiplexed FPGAs [5] --- p.66Chapter 5.5 --- Proposed Net Modelling --- p.70Chapter 5.6 --- Partitioning Properties Based on the Proposed Net Modelling --- p.73Chapter 5.7 --- Partitioning Step --- p.75Chapter 5.8 --- Constrained FM Post Processing Step --- p.79Chapter 5.9 --- Experiment Results --- p.81Chapter 6 --- Conclusion --- p.86Bibliography --- p.8