Journal of Telecommunications and Information Technology, 2018, nr 1

The rearreangeable conditions for the 2×2 three-stage switching fabric of a W-S-W architecture for elastic optical switches are considered in this paper. Analogies between the switching fabric considered and the three-stage Clos network are shown. On the other hand, differences are also shown, which presented the modifications required in the control algorithm used in rearrangeable networks. The rearrangeable conditions and the control algorithm are presented and proved. Operation of the proposed control algorithm is shown based on a few examples. The required number of frequency slot units in interstage links of rearrangeable switching fabrics is much lower than in the strict-sense non-blocking switching fabrics characterized by the same parameters

Study of interconnection networks /

A multi-stage N x N interconnection network is said to be universal if it realizes the set of all permutations on N objects. A new bound on the number of stages required for the universality of shuffle-exchange network as well as the analysis of the combinational power for the block-structured networks are given. Finally, the complexity of the verification of a new sufficient condition for rearrangeability due to Benes B5 is analyzed

Parallel routing algorithms in Benes-Clos networks.

by Soung-Yue Liew.Thesis (M.Phil.)--Chinese University of Hong Kong, 1996.Includes bibliographical references (leaves 55-57).Chapter 1 --- Introduction --- p.1Chapter 2 --- The Basic Principles of Routing Algorithms --- p.10Chapter 2.1 --- The principles of sequential algorithms --- p.11Chapter 2.1.1 --- Edge-coloring of bipartite graph with maximum degree two --- p.11Chapter 2.1.2 --- Edge-coloring of bipartite graph with maximum degree M --- p.14Chapter 2.2 --- Looping algorithm --- p.17Chapter 2.2.1 --- Paull's Matrix --- p.17Chapter 2.2.2 --- Chain to be rearranged in Paull's Matrix --- p.18Chapter 2.3 --- The principles of parallel algorithms --- p.19Chapter 2.3.1 --- Edge-coloring of bipartite graph with maximum degree two --- p.20Chapter 2.3.2 --- Edge-coloring of bipartite graph with maximum degree 2m --- p.22Chapter 3 --- Parallel routing algorithm in Benes-Clos networks --- p.25Chapter 3.1 --- Routing properties of Benes networks --- p.25Chapter 3.1.1 --- Three-stage structure and routing constraints --- p.26Chapter 3.1.2 --- Algebraic interpretation of connection set up problem --- p.29Chapter 3.1.3 --- Equivalent classes --- p.31Chapter 3.2 --- Parallel routing algorithm --- p.32Chapter 3.2.1 --- Basic principles --- p.32Chapter 3.2.2 --- Initialization --- p.34Chapter 3.2.3 --- Algorithm --- p.36Chapter 3.2.4 --- Set up the states and determine π for next stage --- p.37Chapter 3.2.5 --- Simulation results --- p.40Chapter 3.2.6 --- Time complexity --- p.41Chapter 3.3 --- Contention resolution --- p.41Chapter 3.4 --- Algorithms applied to Clos network with 2m central switches --- p.43Chapter 3.5 --- Parallel algorithms in rearrangeability --- p.47Chapter 4 --- Conclusions --- p.5

Symmetric rearrangeable networks and algorithms

A class of symmetric rearrangeable nonblocking networks has been considered in this thesis. A particular focus of this thesis is on Benes networks built with 2 x 2 switching elements. Symmetric rearrangeable networks built with larger switching elements have also being considered. New applications of these networks are found in the areas of System on Chip (SoC) and Network on Chip (NoC). Deterministic routing algorithms used in NoC applications suffer low scalability and slow execution time. On the other hand, faster algorithms are blocking and thus limit throughput. This will be an acceptable trade-off for many applications where achieving ”wire speed” on the on-chip network would require extensive optimisation of the attached devices. In this thesis I designed an algorithm that has much lower blocking probabilities than other suboptimal algorithms but a much faster execution time than deterministic routing algorithms. The suboptimal method uses the looping algorithm in its outermost stages and then in the two distinct subnetworks deeper in the switch uses a fast but suboptimal path search method to find available paths. The worst case time complexity of this new routing method is O(NlogN) using a single processor, which matches the best known results reported in the literature. Disruption of the ongoing communications in this class of networks during rearrangements is an open issue. In this thesis I explored a modification of the topology of these networks which gives rise to what is termed as repackable networks. A repackable topology allows rearrangements of paths without intermittently losing connectivity by breaking the existing communication paths momentarily. The repackable network structure proposed in this thesis is efficient in its use of hardware when compared to other proposals in the literature. As most of the deterministic algorithms designed for Benes networks implement a permutation of all inputs to find the routing tags for the requested inputoutput pairs, I proposed a new algorithm that can work for partial permutations. If the network load is defined as ρ, the mean number of active inputs in a partial permutation is, m = ρN, where N is the network size. This new method is based on mapping the network stages into a set of sub-matrices and then determines the routing tags for each pair of requests by populating the cells of the sub-matrices without creating a blocking state. Overall the serial time complexity of this method is O(NlogN) and O(mlogN) where all N inputs are active and with m < N active inputs respectively. With minor modification to the serial algorithm this method can be made to work in the parallel domain. The time complexity of this routing algorithm in a parallel machine with N completely connected processors is O(log^2 N). With m active requests the time complexity goes down to (logmlogN), which is better than the O(log^2 m + logN), reported in the literature for 2^0.5((log^2 -4logN)^0.5-logN)<= ρ <= 1. I also designed multistage symmetric rearrangeable networks using larger switching elements and implement a new routing algorithm for these classes of networks. The network topology and routing algorithms presented in this thesis should allow large scale networks of modest cost, with low setup times and moderate blocking rates, to be constructed. Such switching networks will be required to meet the bandwidth requirements of future communication networks

Improving the run time of the decomposition algorithm for fault tolerant Clos interconnection networks through swap re-ordering

Clos interconnection networks, used in data networks and computing systems, can contain extra switches to be used in faulty conditions. The speed of such fault tolerant Clos interconnection networks is improved through the use these switches in no-fault situations. The network can be represented by a matrix, which is then decomposed using an algorithm, and the switch settings are thus assigned. The original decomposition algorithm consisted of four element swaps in the following order: wild swap, simple swap, next simple swap, and successive swap. However, by re-arranging these swaps with the simple swap first, followed by the next simple and successive swaps with the wild swap coming either before or after the next simple, the number of total swaps needed to fully decompose the matrix is significantly reduced

Journal of Telecommunications and Information Technology, 2018, nr 1

kwartalni

Devices and networks for optical switching

This thesis is concerned with some aspects of the application of optics to switching and computing. Two areas are dealt with: the design of switching networks which use optical interconnects, and the development and application of the t-SEED optical logic device. The work on optical interconnects looks at the multistage interconnection network which has been proposed as a hybrid switch using both electronics and optics. It is shown that the architecture can be mapped from one dimensional to two dimensional format, so that the machine makes full use of the space available to the optics. Other mapping rules are described which allow the network to make optimum use of the optical interconnects, and the endpoint is a hybrid optical-electronic machine which should be able to outperform an all-electronic equivalent. The development of the t-SEED optical logic device is described, which is the integration of a phototransistor with a multiple quantum well optical modulator. It is found to be important to have the modulator underneath rather than on top of the transistor to avoid unwanted thyristor action. In order for the transistor to have a high gain the collector must have a low doping level, the exit window in the substrate must be etched all the way to the emitter layer, and the etch must not damage the emitter-base junction. A real optical gain of 1.6 has been obtained, which is higher than has ever been reached before but is not as high as should be possible. Improvements to the device are suggested. A new model of the Fabry-Perot cavity is introduced which helps considerably in the interpretation of experimental measurements made on the quantum well modulators. Also a method of improving the contrast of the multiple quantum well modulator by grading the well widths is proposed which may find application in long wavelength transmission modulators. Some systems which make use of the t-SEED are considered. It is shown that the t-SEED device has the right characteristics for use as a neuron element in the optical implementation of a neural network. A new image processing network for clutter removal in binary images is introduced which uses the t-SEED, and a brief performance analysis suggests that the network may be superior to an all-electronic machine

Path switching over multirate Benes network.

Mui Sze Wai.Thesis (M.Phil.)--Chinese University of Hong Kong, 2003.Includes bibliographical references (leaves 62-65).Abstracts in English and Chinese.Chapter 1. --- Introduction --- p.1Chapter 1.1 --- Evolution of Multirate Networks --- p.2Chapter 1.2 --- Some Results from Previous Work --- p.2Chapter 1.3 --- Multirate Traffic on Benes Network --- p.5Chapter 1.4 --- Organization --- p.7Chapter 2. --- Background Knowledge on Benes Network and Path Switching --- p.8Chapter 2.1 --- Benes Network --- p.9Chapter 2.1.1 --- Construction of Large Switching Fabrics --- p.9Chapter 2.1.2 --- Routing in Benes Network --- p.11Chapter 2.1.3 --- Performance when Operated as a Large Switch Fabric --- p.13Chapter 2.2 --- Path Switching --- p.14Chapter 2.2.1 --- Basic Concept of Path Switching --- p.14Chapter 2.2.2 --- Capacity Allocation and Route Assignment --- p.15Chapter 3. --- Path Switching over Benes Network --- p.20Chapter 3.1 --- The Model of path-switched Benes Network --- p.21Chapter 3.2 --- Module-to-Module Implementation --- p.21Chapter 3.2.1 --- The First Stage (Input Module) --- p.22Chapter 3.2.2 --- The Middle Stage (Central Module) --- p.23Chapter 3.2.3 --- The Last Stage (Output Module) --- p.24Chapter 3.3 --- Port-to-Port Implementation --- p.24Chapter 3.3.1 --- Uniform Traffic --- p.25Chapter 3.3.2 --- Mult irate Traffic --- p.26Chapter 3.4 --- Closing remarks --- p.29Chapter 4. --- Performance Analysis --- p.31Chapter 4.1 --- Traffic Constraints and Perform- ance Guarantees --- p.32Chapter 4.1.1 --- Arrival Curve and Service Curve --- p.33Chapter 4.1.2 --- Delay Bound and Backlog Bound --- p.36Chapter 4.2 --- Service Guarantees --- p.39Chapter 4.3 --- Deterministic Bounds --- p.42Chapter 4.3.1 --- Delay --- p.42Chapter 4.3.2 --- Backlog at Input Module --- p.44Chapter 4.3.3 --- Backlog at Output Module --- p.47Chapter 5. --- Simulation Results --- p.52Chapter 5.1 --- Uniform Traffic --- p.53Chapter 5.2 --- Multirate Traffic --- p.55Chapter 6. --- Conclusions and Future Research --- p.59Chapter 6.1 --- Suggestions for future research --- p.61Bibliography --- p.6

Optical Interconnections based on Microring Resonators

Projecte fet en col.laboració amb la Facoltà di Ingegneria dell’Informazione. Politecinco de TorinoThe aim of this thesis is to present and analyse optical interconnection architectures based on microring resonators. The trend of meeting large bandwidth and strict latency requirements in both global on-chip and off-chip communication face critical challenges in maintaining a sustainable performance-per-watt. Optical technologies support the immense bandwidth allowed by wavelength division multiplexed (WDM) while could offer a significant power saving switching capabilities. Microring resonators have received considerable attention as promising technologies for realizing photonic integrated circuits. Their small footprint and their capacity for processing high-bandwidth WDM data can lead these devices become the key elements for the switch nodes in next-generation telecommunication networks. This thesis firstly describes the basic principles of operation of a microring resonator defining 1x2 basic switching element (1B-SE). Then, the 2x2 basic SE (2B-SE) based on two 1B-SEs jointly controlled and the new 2x2 mirrored SE (2M-SE) are characterised as atomic building elements for interconnection architectures. The severe asymmetric behaviour presented by those SEs could limit the scalability of classical optical switching fabrics and we aim at balancing the complexity and optical signal level. In a second stage, the well-known switching theory is revised in order to classify the interconnection architectures according to their characteristics when using that SEs as building element. It is applied an exhaustive procedure to obtain the performance of classical Crossbar and Benes structures and of the newly proposed Mirroring and HBC structures. Thereafter, using as a starting point for each analysed structure the characterisation previously obtained, the scalability response of larger switching fabrics is explored. Then we define a construction rule for the new proposed architectures of which we assess the complexity in terms of used microring

Combinatorial Optimization

This report summarizes the meeting on Combinatorial Optimization where new and promising developments in the field were discussed. Th