4 research outputs found
Recommended from our members
A survey on continuous-time modulators : theory, designs and implementations
Recently, delta-sigma modulation has become a widely applied technique for high-performance analog-to-digital conversion of narrow-band signals. Most of the early designs used discrete-time structure for good accuracy and good linearity. The transfer functions are independent of the clock frequency. However, high unity-gain bandwidths of the opamps are required to satisfy the settling accuracy required in the discrete-time designs. Continuous-time structure can potentially achieve higher clock frequency with less power consumption. the anti-aliasing filter can also be eliminated due to the anti-aliasing property of CT modulators. On the other hand, CT ADC have their own problems, such as jitter sensitivity and excess loop delay. In this thesis, the state-of-the-art of CT modulator is reviewed. The problems in the design of CT ADCs are analyzed and solutions to them are described. The theory, design and implementations of CT modulator will also be reviewed.Keywords: Continuous-Time, Delta-Sigm
Analysis of Current Conveyor based Switched Capacitor Circuits for Application in âÎŁ Modulators
The reduction in supply voltage, loss of dynamic range and increased noise prevent the analog circuits from taking advantage of advanced technologies. Therefore the trend is to move all signal processing tasks to digital domain where advantages of technology scaling can be used. Due to this, there exists a need for data converters with large signal bandwidths, higher speeds and greater dynamic range to act as an interface between real world analog and digital signals.
The Delta Sigma (âÎŁ) modulator is a data converter that makes use of large sampling rates and noise shaping techniques to achieve high resolution in the band of interest. The modulator consists of analog integrators and comparators which create a modulated digital bit stream whose average represents the input value. Due to their simplicity, they are popular in narrow band receivers, medical and sensor applications.
However Operational Amplifiers (Op-Amps) or Operational Transconductance Amplifiers (OTAs), which are commonly used in data converters, present a bottleneck. Due to low supply voltages, designers rely on folded cascode, multistage cascade and bulk driven topologies for their designs. Although the two stage or multistage cascade topologies offer good gain and bandwidth, they suffer from stability problems due to multiple stages and feedback requiring large compensation capacitors. Therefore other low voltage Switched-Capacitor (SC) circuit techniques were developed to overcome these problems, based on inverters, comparators and unity gain buffers.
In this thesis we present an alternative approach to design of âÎŁ modulators using Second Generation Current Conveyors (CCIIs). The important feature of these modulators is the replacement of the traditional Op-Amp based SC integrators with CCII based SC integrators. The main design issues such as the effect of the non-idealities in the CCIIs are considered in the operation of SC circuits and solutions are proposed to cancel them. Design tradeoffs and guidelines for various components of the circuit are presented through analysis of existing and the proposed SC circuits. A two step adaptive calibration technique is presented which uses few additional components to measure the integrator input output characteristic and linearize it for providing optimum performance over a wide range of sampling frequencies while maintaining low power and area.
The presented CCII integrator and calibration circuit are used in the design of a 4th order (2-2 cascade) âÎŁ modulator which has been fabricated in UMC 90nm/1V technology through Europractice. Experimental values for Signal to Noise+Distortion Ratio (SNDR), Dynamic Range (DR) and Figure Of Merit (FOM) show that the modulator can compete with state of art reconfigurable Discrete-Time (DT) architectures while using lower gain stages and less design complexity
Providing Bi-Directional, Analog, and Differential Signal Transmission Capability to an Electronic Prototyping Platform
RĂSUMĂ Les rĂ©seaux dâinterconnexions programmables (FPIN) se retrouvent largement utilisĂ©s dans plusieurs structures bien connues telles que les FPGA, les plateformes de prototypages ainsi que dans plusieurs architectures de rĂ©seaux intĂ©grĂ©s. Le but de la prĂ©sente thĂšse est dâamĂ©liorer la structure actuelle des FPIN ainsi que les plateformes de prototypages se basant sur cette technologie afin dây intĂ©grer dâautres fonctionnalitĂ©s telles que des interfaces pour les signaux bidirectionnels de type drain-ouvert, les signaux analogiques ou bien les signaux diïŹĂ©rentiels. Cette thĂšse prĂ©sente trois diïŹĂ©rents circuits qui ont Ă©tĂ© implĂ©mentĂ©s dans cette optique. Les interconnexions de ces trois circuits peuvent ĂȘtre reconfigurĂ©es pour supporter une interface de type bidirectionnelle drain-ouvert, de type analogique ou diïŹĂ©rentielle, le tout au travers un rĂ©seau dâinterconnexions configurable numĂ©rique unidirectionnel, ou FPIN. Le besoin dâune telle interface fut tout dâabord envisagĂ© dans le contexte du WaferBoard, qui consiste en une plateforme reconfigurable de prototypage pour les systĂšmes Ă©lectroniques. Le cĆur de ce WaferBoard consiste en un circuit intĂ©grĂ© Ă lâĂ©chelle dâune tranche entiĂšre de silicium, qui est constituĂ© dâune matrice bidimensionnelle de cellules. Une large partie de la surface disponible sâen retrouve dĂ©jĂ utilisĂ©e par des plots configurables (CIO), lâaiguillage des multiplexeurs du FPIN, des registres dĂ©diĂ©s Ă la chaine JTAG et dâautres circuiteries de contrĂŽle. De ce fait, il en devient primordial que les interfaces bidirectionnelle drain-ouvert, analogique et diïŹĂ©rentielle soit les plus compactes possibles. Puisque ces circuits dâinterfaces seront dĂ©diĂ©s pour une plateforme utilisant une tranche de silicium (wafer-scale), lâarchitecture de ces derniers doit ĂȘtre robuste en regard des variations de procĂ©dĂ©, de la tempĂ©rature ainsi que de lâalimentation. La premiĂšre contribution de cette thĂšse est lâĂ©laboration et la conception dâune interface de type drain-ouvert ainsi que de son support dâinterconnexion bidirectionnel utilisant un rĂ©seau numĂ©rique unidirectionnel Ă signalisation asymĂ©trique (Ă lâopposĂ© de la signalisation diïŹĂ©rentielle) FPIN. Lâinterface proposĂ©e peut interconnecter plusieurs nĆuds dâun FPIN. Ă lâaide de cette interface, le rĂ©seau dâinterconnexions peut imiter le comportement et le fonctionnement dâun bus de type drain-ouvert (ou collecteur-ouvert) (tel quâutilisĂ© par le protocole I2C). De ce fait, plusieurs plots de type drain-ouvert provenant dâune multitude de circuits-intĂ©grĂ©s (ICs) diïŹĂ©rents peuvent y ĂȘtre connectĂ©s au travers le FPIN Ă lâaide de lâinterface proposĂ©e.----------ABSTRACT Field programmable interconnection networks (FPINs) are ubiquitously found embedded in field-programmable gate arrays (FPGAs), in prototyping platforms, and in many Network-on-Chip architectures. The aim of this research was to augment the application domains of current FPIN-based prototyping and emulation platforms by supporting open-drain bi-directional signals, analog signals or diïŹerential signals. Three interface circuits have been elaborated and developed to that end in this thesis. These three interface circuits can support reconfigurable routing of open-drain bi-directional, analog and diïŹerential signals through an uni-directional digital FPIN. The need for such interface circuits were originally conceived in the context of the WaferBoard, a system prototyping platform. The core of the WaferBoard is a wafer-scale IC that is composed of a two dimensional array of unit cells. Available area was already over-utilized by the configurable I/O (CIO) buïŹers, crossbar multiplexers of the FPIN, registers of the JTAG chain, and other control circuits. Thus, the interface circuits for open-drain bi-directional, analog and diïŹerential signaling had to be made very compact. As the implementation of these interface circuits target âwafer-scaleâ integration, these interface circuits had to be very robust to parametric variations (process, temperature, power supply). The first contribution of this thesis is the elaboration and development of an open-drain interface circuit and a corresponding interconnect topology to support bi-directional communication through the uni-directional digital FPIN of prototyping platforms. The proposed interface can interconnect multiple nodes in a FPIN. With that interface, the interconnection network imitates the behavior of open-drain (or open-collector) buses (e.g., those following the I2C protocol). Thus, multiple open-drain I/Os from external integrated circuits (ICs) can be connected together through the FPIN by the proposed interface circuit. The interface that has been fabricated in a 0.13 ”m CMOS technology takes 65 ”m Ă 22 ”m per pin. Test results show that several instances of this interface can be interconnected through the proposed interconnect topology