A \u3cem\u3eK\u3c/em\u3e-Delta-1-Sigma Modulator for Wideband Analog to Digital Conversion

As CMOS technology shrinks, the transistor speed K-quantizing paths and can achieve significantly higher conversion bandwidths when compared to the traditional deltasigma ADCs. The 8-path KD1S modulator achieves an SNR of 58 dB (or 9.4-bits resolution) when clocked at 100 MHz for a conversion bandwidth of 6.25 MHz and an effective sampling rate equal to 800 MHz. The KD1S modulator has been fabricated in a 500 nm CMOS process and the experimental results are reported. Deficiencies in the first test chip performance are discussed along with their alleviation to achieve theoretical performance

Free Level Threshold Zone (FLTZ) Logic For Mixed Analog-Digital Closed Loop Circuitry [TK7887.6. N335 2008 f rb].

Para penyelidik sentiasa mencari cara-cara penambahbaikan kaedah antara muka antara domain Analog dan Digital. Researchers have always look for ways to improve the interfacing method between the Analog and Digital domain

Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI

First order sigma-delta modulator of an oversampling ADC design in CMOS using floating gate MOSFETS

We report a new architecture for a sigma-delta oversampling analog-to-digital converter (ADC) in which the first order modulator is realized using the floating gate MOSFETs at the input stage of an integrator and the comparator. The first order modulator is designed using an 8 MHz sampling clock frequency and implemented in a standard 1.5µm n-well CMOS process. The decimator is an off-chip sinc-filter and is programmed using the VERILOG and tested with Altera Flex EPF10K70RC240 FPGA board. The ADC gives an 8-bit resolution with a 65 kHz bandwidth

Sparsity-Aware Low-Power ADC Architecture with Advanced Reconstruction Algorithms

Compressive sensing (CS) technique enables a universal sub-Nyquist sampling of sparse and compressible signals, while still guaranteeing the reliable signal recovery. Its potential lies in the reduced analog-to-digital conversion rate in sampling broadband and/or multi-channel sparse signals, where conventional Nyquist-rate sampling are either technology impossible or extremely hardware costly. Nevertheless, there are many challenges in the CS hardware design. In coherent sampling, state-of-the-art mixed-signal CS front-ends, such as random demodulator and modulated wideband converter, suffer from high power and nonlinear hardware. In signal recovery, state-of-the-art CS reconstruction methods have tractable computational complexity and probabilistically guaranteed performance. However, they are still high cost (basis pursuit) or noise sensitive (matching pursuit). In this dissertation, we propose an asynchronous compressive sensing (ACS) front-end and advanced signal reconstruction algorithms to address these challenges. The ACS front-end consists of a continuous-time ternary encoding (CT-TE) scheme which converts signal amplitude variations into high-rate ternary timing signal, and a digital random sampler (DRS) which captures the ternary timing signal at sub-Nyquist rate. The CT-TE employs asynchronous sampling mechanism for pulsed-like input and has signal-dependent conversion rate. The DRS has low power, ease of massive integration, and excellent linearity in comparison to state-of-the-art mixed-signal CS front-ends. We propose two reconstruction algorithms. One is group-based total variation, which exploits piecewise-constant characteristics and achieves better mean squared error and faster convergence rate than the conventional TV scheme with moderate noise. The second algorithm is split-projection least squares (SPLS), which relies on a series of low-complexity and independent l2-norm problems with the prior on ternary-valued signal. The SPLS scheme has good noise robustness, low-cost signal reconstruction and facilitates a parallel hardware for real-time signal recovery. In application study, we propose multi-channel filter banks ACS front-end for the interference-robust radar. The proposed receiver performs reliable target detection with nearly 8-fold data compression than Nyquist-rate sampling in the presence of -50dBm wireless interference. We also propose an asynchronous compressed beamformer (ACB) for low-power portable diagnostic ultrasound. The proposed ACB achieves 9-fold data volume compression and only 4.4% contrast-to-noise ratio loss on the imaging results when compared with the Nyquist-rate ADCs

Study of SAW resonator based band pass delta-sigma modulators

Master'sMASTER OF ENGINEERIN

DESIGN OF THE TRANSCONDUCTANCE AMPLIFIER FOR FREQUENCY DOMAIN SAMPLING RECEIVER

In this work, the circuit implementation of the front-end for Frequency Domain (FD) Sampling Receiver is presented. Shooting for two different applications, two transconductance amplifiers are designed. A high linear transconductance amplifier with 25 dBm IIP3 is proposed to form the high resolution and high sampling rate FD receiver. The whole system achieves an overall sampling rate of 2 Gs/s and resolution of 10 bits. Another low noise transconductance amplifier exploiting noise cancelling is designed to build up the FD wireless communication receiver, which is an excellent candidate for Software Define Radio (SDR) and Cognitve Radio (CR). The proposed noise cancelling scheme can suppress both thermal noise and flicker noise at the frontend. The system Noise Figure (NF) is improved by 3.28 dB. The two transconductance amplifiers are simulated and fabricated with TI 45nm CMOS technology

A 90.5dB DR 1MHz BW Hybrid Two Step ADC with CT Incremental and SAR ADCs

The sensors in real time data processing IoT devices require high resolution and sub-MHz data converters, usually implemented as Incremental ADCs due to the advantages of oversampling technique and low latency. In discrete time incremental (IDT) ADCs, the sampling switch non-linearity, charge injection degrade the resolution, and power hungry OPAMPs are demanded to provide fast and accurate settling for the switch-capacitor circuits. While the continuous time incremental (ICT) ADCs overcome these issues by removing the sampling switches and it also relax the OPAMPs settling accuracy to save power. A hybrid architecture of ICT ADC and SAR two step ADC is proposed to achieve high resolution at low oversampling ratio (OSR). The first ICT ADCs enable higher resolution, faster conversion speed with lower power consumption. The residual error of the ICT ADC is extracted at the last integrator output and transfers to the 2nd SAR for further conversion. In this architecture, only the mismatch between the cascade of integrators (CoIs) and decimation filter transfer functions causes 1st stage quantization noise leakage which can be solved by increasing opamp parameters instead of increasing the digital decimation filter complexity. In addition, the overall SQNR is independent of the first ICT ADC’s NTF, which gives more freedom to trade-off between the loop stability and DAC errors. A 4bits DRZ DAC with data weighted averaging (DWA) technique is adopted to reduce the clock jitter of DAC, mitigate ISI error and static mismatch errors. Based on this architecture, a 16b resolution, 1MHz signal bandwidth hybrid two step ADC is designed and measurement results are demonstrated. Important sub circuits are introduced and analyzed in detail to get the target resolution. The ADC is fabricated in AKM 180nm CMOS process with 1.8V supply voltage, it achieves a DR of 90.5dB, and SNR/SFDR/SNDR of 82.5dB/85dB/80.5dB over 1MHz BW sampled at 64MHz