A Low-Voltage Electronically Tunable MOSFET-C Voltage-Mode First-Order All-Pass Filter Design

This paper presents a simple electronically tunable voltage-mode first-order all-pass filter realization with MOSFET-C technique. In comparison to the classical MOSFET-C filter circuits that employ active elements including large number of transistors the proposed circuit is only composed of a single two n-channel MOSFET-based inverting voltage buffer, three passive components, and one NMOS-based voltage-controlled resistor, which is with advantage used to electronically control the pole frequency of the filter in range 103 kHz to 18.3 MHz. The proposed filter is also very suitable for low-voltage operation, since between its supply rails it uses only two MOSFETs. In the paper the effect of load is investigated. In addition, in order to suppress the effect of non-zero output resistance of the inverting voltage buffer, two compensation techniques are also introduced. The theoretical results are verified by SPICE simulations using PTM 90 nm level-7 CMOS process BSIM3v3 parameters, where +/- 0.45 V supply voltages are used. Moreover, the behavior of the proposed filter was also experimentally measured using readily available array transistors CD4007UB by Texas Instruments

Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing

With advancing process technologies and booming IoT markets, millimeter-wave CMOS RFICs have been widely developed in re- cent years. Since the performance of CMOS RFICs is very sensi- tive to the precision of the layout, precise placement of devices and precisely matched microstrip lengths to given values have been a labor-intensive and time-consuming task, and thus become a major bottleneck for time to market. This paper introduces a progressive integer-linear-programming-based method to gener- ate high-quality RFIC layouts satisfying very stringent routing requirements of microstrip lines, including spacing/non-crossing rules, precise length, and bend number minimization, within a given layout area. The resulting RFIC layouts excel in both per- formance and area with much fewer bends compared with the simulation-tuning based manual layout, while the layout gener- ation time is significantly reduced from weeks to half an hour.Comment: ACM/IEEE Design Automation Conference (DAC), 201

A 64-channel, 1.1-pA-accurate on-chip potentiostat for parallel electrochemical monitoring

Electrochemical monitoring is crucial for both industrial applications, such as microbial electrolysis and corrosion monitoring as well as consumer applications such as personal health monitoring. Yet, state-of-the-art integrated potentiostat monitoring devices have few parallel channels with limited flexibility due to their channel architecture. This work presents a novel, widely scalable channel architecture using a switch capacitor based Howland current pump and a digital potential controller. An integrated, 64-channel CMOS potentiostat array has been fabricated. Each individual channel has a dynamic current range of 120dB with 1.1pA precision with up to 100kHz bandwidth. The on-chip working electrodes are post-processed with gold to ensure (bio)electrochemical compatibility

Phase and amplitude pre-emphasis techniques for low-power serial links

A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-dependent jitter. Phase pre-emphasis augments the performance of low power transmitters in bandwidth-limited channels. The transmitter circuit is implemented in a 90-nm bulk CMOS process and reduces power consumption by pushing CMOS static logic to the output stage, a 4:1 output multiplexer. The received signal jitter over a cable is reduced from 16.15 ps to 10.29 ps with only phase pre-emphasis at the transmitter. The jitter is reduced by 3.6 ps over an FR-4 backplane interconnect. A transmitter without phase pre-emphasis consumes 18 mW of power at 6Gb/s and 600mVpp output swing, a power budget of 3mW/Gb/s, while a transmitter with phase pre-emphasis consumes 24mW, a budget of 4 mW/Gb/s

A 1.6 Gb/s, 3 mW CMOS receiver for optical communication

A 1.6 Gb/s receiver for optical communication has been designed and fabricated in a 0.25-μm CMOS process. This receiver has no transimpedance amplifier and uses the parasitic capacitor of the flip-chip bonded photodetector as an integrating element and resolves the data with a double-sampling technique. A simple feedback loop adjusts a bias current to the average optical signal, which essentially "AC couples" the input. The resulting receiver resolves an 11 μA input, dissipates 3 mW of power, occupies 80 μm x 50 μm of area and operates at over 1.6 Gb/s

An Ultra-Low-Power Oscillator with Temperature and Process Compensation for UHF RFID Transponder

This paper presents a 1.28MHz ultra-low-power oscillator with temperature and process compensation. It is very suitable for clock generation circuits used in ultra-high-frequency (UHF) radio-frequency identification (RFID) transponders. Detailed analysis of the oscillator design, including process and temperature compensation techniques are discussed. The circuit is designed using TSMC 0.18μm standard CMOS process and simulated with Spectre. Simulation results show that, without post-fabrication calibration or off-chip components, less than ±3% frequency variation is obtained from –40 to 85°C in three different process corners. Monte Carlo simulations have also been performed, and demonstrate a 3σ deviation of about 6%. The power for the proposed circuitry is only 1.18µW at 27°C

Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA) based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends

Variation Resilient Adaptive Controller for Subthreshold Circuits

Subthreshold logic is showing good promise as a viable ultra-low-power circuit design technique for power-limited applications. For this design technique to gain widespread adoption, one of the most pressing concerns is how to improve the robustness of subthreshold logic to process and temperature variations. We propose a variation resilient adaptive controller for subthreshold circuits with the following novel features: new sensor based on time-to-digital converter for capturing the variations accurately as digital signatures, and an all-digital DC-DC converter incorporating the sensor capable of generating an operating operating Vdd from 0V to 1.2V with a resolution of 18.75mV, suitable for subthreshold circuit operation. The benefits of the proposed controller is reflected with energy improvement of up to 55% compared to when no controller is employed. The detailed implementation and validation of the proposed controller is discussed

DCCII-Based Novel Lossless Grounded Inductance Simulators With No Element Matching Constrains

In 1996, the differential current conveyor (DCCII) was introduced as a versatile active element with current differencing capability. Therefore, in this study, the usefulness of the DCCII is shown on six novel lossless grounded inductance simulator circuits. Proposed circuits simultaneously employ minimum number of elements, i.e. single DCCII, one capacitor, and two resistors. No passive element matching restriction is needed and all solutions are electronically tunable in case that one of resistors is replaced by MOSFET-based voltage-controlled resistor. The internal structure of the active element has been implemented using the TSMC 0.25 um SCN025 CMOS process BSIM3v3.1 parameters. Firstly, the performance of the selected inductor simulator is evaluated and subsequently verified in the design of 5th-order high-pass ladder and 2nd-order frequency filters. In addition, experimental results using commercially available AD844/ADs are given to verify the theoretical analysis and SPICE simulations