Implementation of 4-BIT ALU with GCD

This work deals with the implementation of a ALU Processor with GCD using Xilinx ISE 9.1i and Spartan 3 FPGA kit. The GCD processor has been implemented using Euclid’s algorithm. ALU performs arithmetic operations and logical operations. Code is dumped on FPGA kit and output is analyzed. The select line is used to decide the whether which operation to perform either GCD or ALU. The work also involves the simulation of the work on Xilinx ISE 9.1i. The implemented program was simulated and output waveforms were observed. We are using Spartan 3 FPGA board for observing the output. The program is dumped using JTAG( Joint Test Action Group) cable on the FPGA Board. DOI: 10.17762/ijritcc2321-8169.150317

Advanced photonic and electronic systems WILGA 2018

WILGA annual symposium on advanced photonic and electronic systems has been organized by young scientist for young scientists since two decades. It traditionally gathers around 400 young researchers and their tutors. Ph.D students and graduates present their recent achievements during well attended oral sessions. Wilga is a very good digest of Ph.D. works carried out at technical universities in electronics and photonics, as well as information sciences throughout Poland and some neighboring countries. Publishing patronage over Wilga keep Elektronika technical journal by SEP, IJET and Proceedings of SPIE. The latter world editorial series publishes annually more than 200 papers from Wilga. Wilga 2018 was the XLII edition of this meeting. The following topical tracks were distinguished: photonics, electronics, information technologies and system research. The article is a digest of some chosen works presented during Wilga 2018 symposium. WILGA 2017 works were published in Proc. SPIE vol.10445. WILGA 2018 works were published in Proc. SPIE vol.10808

A Novel Approach for Integrated Shortest Path Finding Algorithm (ISPSA) Using Mesh Topologies and Networks-on-Chip (NOC)

A novel data dispatching or communication technique based on circulating networks of any network IP is suggested for multi data transmission in multiprocessor systems using Networks-On-Chip (NoC). In wireless communication network management have some negatives have heavy data losses and traffic of data sending data while packet scheduling and low performance in the varied network due to workloads. To overcome the drawbacks, in this method proposed system is Integrated Shortest Path Search Algorithm (ISPSA) using mesh topologies. The message is sent to IP (Internet Protocol) in the network until the specified bus accepts it. Integrated Shortest Path Search Algorithm for communication between two nodes is possible at any one moment. On-chip wireless communications operating at specific frequencies are the most capable option for overcoming metal interconnects multi-hop delay and excessive power consumption in Network-on-Chip (NoC) devices. Each node can be indicated by a pair of coordinates (level, position), where the level is the tree's vertical level and the view point is its horizontal arrangement in the sequence of left to right. The output gateway node's n nodes are linked to two nodes in the following level, with all resource nodes located at the bottommost vertical level and the constraint of this topology is its narrow bisection area. The software Xilinx 14.5 tool by using that overall performance analysis of mesh topology, each method are reduced data losses with better accuracy although the productivity of the delay is decreased by 21 % was evaluated and calculated.

Implementation Of FPGA Based Encryption Chip Using VHD - Data Encryption Standard (DES) Algorithm

Cryptography has a long and fascinating history. Traditional Encryption Algorithms are implemented in software base because of the complexities involved in the operations. The hardware based of encryption chip become realizable with Field Programmable Gate Arrays (FPGAs). There are many researchers used Data Encryption Standard (DES) Algorithm to implement in FPGAs. The purpose of this project is to implement FPGA Base Encryption Chip using DES algorithm. Throughout the project, the suitability of the implementation DES algorithm in FPGA will be investigated. The first stage of this project is to understand the algorithm flow of the DES. In second stage, the system is described using Very High Speed Integrated Circuits hardware description language (VHDL). In third stage, compilation and simulation for source code verification purpose is done to yield the correct output by using Altera Quartus II 5.0 software. Result shows that DES algorithm can be implementing in Altera UP2 Board. The final product of this project is a FPGA DES Encryption Chip that is capable to encrypt or decrypt 64-bit blocks with 64-bit key. It has a simple architecture, high accuracy, high applicability and high speed. The maximum possible frequency can be used for the system is 29.33 MHz and the total of logic element used is only 708LE

Design Of FPGA-Based Encryption Chipusing Blowfish Algorithm

Nowadays, the world has changed so rapidly that everything has become digitized and computerized. Unfortunately, digital information is very easy to be duplicated, modified, transmitted or used by unauthorized users. This results a serious problem and in view of this, some sort of security mechanism has to be produced to protect it. This is where the study of cryptography comes in. Cryptography has been introduced to protect the information. However, until now, the cryptography hardware is still not commonly used especially in FPGA. In this project, the Blowfish encryption algorithm is chosen because it is among the safest algorithm used nowadays. The aim of this project is to design a Blowfish encryption chip in FPGA. For this project, the design entry used is Altera’s Quartus II Version 5.0 and the targeted hardware is Altera’s Flex10K FPGA device. By using FPGA device, data can be encrypted or decrypted in real time and this would be a great tool for security purpose, such as ATM machine. The first stage of this project is the study of Blowfish algorithm and translates the method into VHDL code because VHDL has been commonly used as a design entry language for FPGA in digital design. Producing the VHDL code is the most difficult and time-consuming part throughout this project. In the second stage, the design is realized using the FPGA board. In this stage, timing is the most critical factor that must be taken care of. If the timing is incorrect, the output may be wrong. Comparison will be done on the software result and hardware result to ensure that the encryption chip is designed correctly and function well

FPGA Implementation using VHDL of the AES-GCM 256-bit Authenticated Encryption Algorithm

Η επίτευξη υψηλών ταχυτήτων μετάδοσης δεδομένων στα τηλεπικοινωνιακά δίκτυα μαζί με την ανάγκη για αξιόπιστη και ασφαλή μετάδοση των πληροφοριών ήταν πάντα μια πρόκληση. Η ανάγκη για επικοινωνία μέσο δημόσιων δικτύων με ασφαλή τρόπο, οδήγησε στην χρήση αλγόριθμων κρυπτογράφηση ασύμμετρου κλειδιού, οπού ένας μηχανισμός «χειραψίας» εξασφαλίζει την ασφαλή μετάδοση δεδομένων και την ακεραιότητα αυτών. Παρόλο που μαθηματικά δεν έχει αποδειχτεί ότι αυτοί οι αλγόριθμοι είναι άτρωτοι σε κρυπτογραφικές επιθέσεις, υπάρχουν ισχυρές ενδείξεις ότι είναι ανθεκτικοί στις περισσότερες κάνοντας την επίθεση ωμής βίας (bruteforce) την μόνη που έχει 100% πιθανότητα επιτυχίας δεδομένης τεράστιας υπολογιστικής ισχύος. Ενώ οι αλγόριθμοι ασύμμετρου κλειδιού ήταν η λύση για τις δημόσιες επικοινωνίες, η συνεχής απαίτηση για μεγαλύτερο εύρος ζώνης, έκανε την χρήση τους μη αποδοτική λόγο του υψηλού κόστους που απαιτούν σε υπολογιστική ισχύ. Η λύση στο πρόβλημα ήρθε με την υβριδική χρήση αλγορίθμων συμμετρικού και ασύμμετρου κλειδιού, έτσι ώστε να διατηρείτε ασφαλή μεταφορά δεδομένων αλλά η ταχύτητα επεξεργασίας των δεδομένων να αυξηθεί σημαντικά. Η ανάλυση στους συμμετρικούς αλγόριθμους οδήγησε στην δημιουργία του αλγορίθμου κρυπτογράφησης Advanced Encryption Standard (AES) που δημοσιεύτηκε από τον οργανισμό NIST το 2001, ως διάδοχο του DES. Η ανάγκη για αυθεντικοποίηση των δεδομένων οδήγησε στην δημιουργίας του αλγορίθμου GCM όπου μπορεί να αυθεντικοποιήσει μια ροή δεδομένων με αξιόπιστο και αποδοτικό τρόπο. Και οι δύο αλγόριθμοι έχουν το πλεονέκτημα ότι μπορεί να υλοποιηθούν εύκολα τόσο σε λογισμικό όσο και σε υλικό. Με την ζήτηση για υψηλές ταχύτητες να είναι μεγάλη, η υλοποίηση σε υλικό γίνεται μια όλο και πιο ελκυστική επιλογή. Οι πυρήνες IP με βάση την τεχνολογία FPGA μπορούν να υλοποιήσουν αυτούς τους αλγόριθμους με την χρήση γλωσσών περιγραφής υλικού όπως η VHDL,και να προσφέρουν αξιόπιστη και υψηλών ταχυτήτων επεξεργασία δεδομένων. Σε αυτή την εργασία σχεδιάσαμε χρησιμοποιώντας την γλώσσα VHDL και υλοποιήσαμε στο FPGA Virtex 5 XC5VFX130T της Xilinx, τον αλγόριθμό κρυπτογράφησης AES με το πρωτόκολλο αυθεντικοποίησης GCM, με μέγεθος κλειδιού στα 256 bits. Η υλοποίηση μας βασίζεται σε μια μη σωληνομένη εκδοχή του αλγορίθμου AES που μπορεί να κρυπτογραφήσει ένα μπλοκ 128 bits σε 15 κύκλους. Η αυθεντικοποίηση του μηνύματος μπορεί να επιτευχθεί σε 16 κύκλους. Η υλοποίηση μας με IV = 96 bits και παράλληλο πολλαπλασιαστή χρειάζεται 5% από τα slices και 1% από τα BRAMs του Virtex-5 XC5VFX130T FPGA. Η μέγιστη δυνατή συχνότητα είναι 227.690 MHz.Achieving high-speed network performance along with data integrity and security was always a challenge. The necessity to communicate through public channels securely led to the use of asymmetric key cryptography algorithms that commonly use a “hand-shake” mechanism allowing the implementation of a “trust” system that could quarantine the security of the transaction and the integrity of the data as long as the algorithm could provide strong resistance to cryptographic attacks. Although, there is no mathematical proof that these algorithms are invulnerable to attacks there is strong indication that they are highly resistant to most of them, making brute force the only attack that can have a 100% success rate which is countered by the huge computational power someone needs to succeed. While asymmetric key cryptography algorithms where the solution to public communication, the ongoing demand for higher bandwidth made the use of them inefficient, because the complexity of the algorithms demanded a processing cost that were creating latency gaps. A solution to this problem was the use of symmetric key algorithms for data transactions were the processing cost is much lower, so that the transaction security was intact but the bottleneck on the encryption/decryption speed limit was increased. The analysis in symmetric cryptographic algorithms resulted in the creation of the Advanced Encryption Standard (AES) published by NIST in 2001. Also the need of authentication and integrity of information transmitted, resulted in the creation of the AES-GCM mode which can authenticate a stream of data (up to 68Gb) with reliable and efficient way. Both algorithms have the advantage to be easily implemented in both software and hardware. With the demand of high speed interaction between networks and systems, it became clear that hardware solutions were the leading option to cover this demand. FPGA-based IP cores can implement those algorithms, with the use of hardware description language like VHDL, and provide accurate, reliable and high speed data process. In this thesis, we have designed in VHDL and implemented in Xilinx Virtex-5 FPGA technology an AES-GCM algorithm that performs authenticated encryption with an encryption key of 256 bits. Our AES-GCM implementation utilizes a non-pipelined version of the AES core and needs 15 cycles to encrypt 128-bits of plaintext, which is the minimum encryption duration supported without pipelining. Concerning the authentication process, our IP core can complete the authenticate process in 16 cycles. Our implementation of the AES-GCM algorithm with AES key = 256 bit, initialization vector (IV) vector = 96 bit, and a full parallel GHASH multiplier on a Xilinx’s Virtex-5 XC5VFX130T FPGA that is pin-to-pin compatible with the Space-grade Xilinx’s Virtex-5QV FPGA requires 5% of slices and 1% of BRAMs. The maximum achievable clock frequency is 227.690 MHz

Static Analysis of Circuits for Security

The purpose of the present work is to define a methodology to analyze a system description given in VHDL code and test its security properties. In particular the analysis is aimed at ensuring that a malicious user cannot make a circuit output the secret data it contains

9/7 LIFT Reconfigurable Architecture Implementation for Image Authentication

Considering the information system medical images are the most sensitive and critical types of data. Transferring medical images over the internet requires the use of authentication algorithms that are resistant to attacks. Another aspect is confidentiality for secure storage and transfer of medical images. The proposed study presents an embedding technique to improve the security of medical images. As a part of preprocessing that involves removing the high-frequency components, Gaussian filters are used. To get LL band features CDF9/7 wavelet is employed. In a similar way, for the cover image, the LL band features are obtained. In order to get the 1st level of encryption the technique of alpha blending is used. It combines the LL band features of the secret image and cover images whereas LH, HL, and HH bands are applied to Inverse CDF 9/7. The resulting encrypted image along with the key obtained through LH, HL, and HH bands is transferred. The produced key adds an extra layer of protection, and similarly, the receiver does the reverse action to acquire the original secret image. The PSNR acquired from the suggested technique is compared to PSNR obtained from existing techniques to validate the results. Performance is quantified in terms of PSNR. A Spartan 6 FPGA board is used to synthesize the complete architecture in order to compare hardware consumption

Memory-Based High-Level Synthesis Optimizations Security Exploration on the Power Side-Channel

High-level synthesis (HLS) allows hardware designers to think algorithmically and not worry about low-level, cycle-by-cycle details. This provides the ability to quickly explore the architectural design space and tradeoffs between resource utilization and performance. Unfortunately, security evaluation is not a standard part of the HLS design flow. In this article, we aim to understand the effects of memory-based HLS optimizations on power side-channel leakage. We use Xilinx Vivado HLS to develop different cryptographic cores, implement them on a Spartan-6 FPGA, and collect power traces. We evaluate the designs with respect to resource utilization, performance, and information leakage through power consumption. We have two important observations and contributions. First, the choice of resource optimization directive results in different levels of side-channel vulnerabilities. Second, the partitioning optimization directive can greatly compromise the hardware cryptographic system through power side-channel leakage due to the deployment of memory control logic. We describe an evaluation procedure for power side-channel leakage and use it to make best-effort recommendations about how to design more secure architectures in the cryptographic domain