Removal of nitrogen pollutant from domestic wastewater

Water as a medium for waste transport would be easily contaminated by human activities. Many methods have been proposed to treat contaminated water to protect human health and biodiversity (Z. Daud et al., 2017). Due to upgrade the existing wastewater treatment plant facilities, the typically advanced technologies have been proposed to remove many types of pollutant, effectively (Tchobanoglous, Burton, & Stensel, 2004). The development of wastewater treatment plant needs to be considered leading economic indicators to have low operational and maintenance costs (Lewandowski, 2015; Shammas, Wang, & Wu, 2009). Aerobic digestion (AD) has been known since 1950 as biological wastewater treatment process to treat wastewater by removing the pollutants for instance colloids, organic compounds and suspended solids to avoid the excessive pollutants released into the receiving water (Shammas and Wang, 2007)

Kesan aplikasi pembelajaran berteraskan multimedia terhadap pelajar teknikal dari aspek gaya pembelajaran visual di politeknik Malaysia

Visual dalam pendidikan adalah pendekatan yang mampu melatih keupayaan pelajar untuk memahami sesuatu konsep pembelajaran yang baru dengan mudah mahupun meningkatkan tahap pemahaman. Kajian ini adalah bertujuan untuk mengenalpasti perkaitan diantara penggunaan aplikasi pembelajaran dengan gaya pembelajaran visual pelajar dalam matapelajaran Computer Networking Fundamentals. Responden kajian ini adalah terdiri daripada pelajar semester 5 daripada 2 buah Politeknik iaitu Politeknik Ibrahim Sultan, Johor, dan Politeknik Port Dickson, Negeri Sembilan yang mengambil matapelajaran Computer Networking Fundamentals (EC301) . Seramai 19 responden yang diambil sebagai kumpulan rawatan daripada Politeknik Ibrahim Sultan (PIS) dan seramai 21 responden lagi berfungsi sebagai kumpulan kawalan daripada Politeknik Port Dickson (PPD). Terdapat 3 instrumen yang digunakan untuk menjalankan kajian ini. Instrumen pertama adalah aplikasi pembelajaran bagi matapelajaran Computer Networking Fundamentals (EC301) yang digunakan oleh kumpulan rawatan, borang kaji selidik untuk mengenalpasti gaya pembelajaran setiap responden, dan intrumen yang ketiga adalah set ujian penilaian (ujian pra dan ujian pasca) bagi menilai tahap pencapaian kesemua responden. Data dianalisis menggunakan Analisis ANCOVA dan hasil kajian mendapati bahawa, pelajar yang menggunakan aplikasi pembelajaran dan disesuaikan dengan gaya pembelajaran visual (A_V) mencapai skor min markah yang paling tinggi iaitu 10.194 berbanding dengan kategori pelajar yang bukan bergaya pembelajaran visual dan tidak menggunakan aplikasi pembelajaran yang masing-masing hanya mencapai skor min 9.417 (A_BV), 4.950 (BA_BV) dan 3.646 (BA_V). Berasaskan kepada hasil dapatan ini, satu kerangka perlaksanaan telah di syorkan dengan menggabungkan intervensi aplikasi pembelajaran dengan elemen gaya pembelajaran visual bagi meningkatkan daya kefahaman pelajar semasa proses pengajaran dan pembelajaran

Hand-arm vibration disorder among grass-cutter workers in Malaysia

Prolonged exposure to hand-transmitted vibration from grass-cutting machines has been associated with increasing occurrences of symptoms and signs of occupational diseases related to hand-arm vibration syndrome (HAVS). Methods. A cross-sectional study was carried out using an adopted HAVS questionnaire on hand-arm vibration exposure and symptoms distributed to 168 male workers from the grass and turf maintenance industry who use hand-held grass-cutting machines as part of their work. The prevalence ratio and symptom correlation to HAVS between high and low–moderate exposure risk groups were evaluated. Results. There were positive HAVS symptoms relationships between the low–moderate exposure group and the high exposure group among hand-held grass-cutting workers. The prevalence ratio was considered high because there were indicators that fingers turned white and felt numb, 3.63, 95% CI [1.41, 9.39] and 4.24, 95% CI [2.18, 8.27], respectively. Less than 14.3% of workers stated that they were aware of the occupational hand-arm vibration, and it seemed to be related to the finger blanching and numbness. Conclusion. The results suggest that HAVS is under-diagnosed in Malaysia, especially in the agricultural sectors. More information related to safety and health awareness programmes for HAVS exposure is required among hand-held grass-cutting workers

64 x 64 Bit Multiplier Using Pass Logic

ABSTRACT Due to the rapid progress in the field of VLSI, improvements in speed, power and area are quite evident. Research and development in this field are motivated by growing markets of portable mobile devices such as personal multimedia players, cellular phones, digital camcorders and digital cameras. Among the recently popular logic families, pass transistor logic is promising for low power applications as compared to conventional static CMOS because of lower transistor count. This thesis proposes four novel designs for Booth encoder and selector logic using pass logic principles. These new designs are implemented and used to build a 64 x 64-bit multiplier. The proposed Booth encoder and selector logic are competitive with the existing and shows substantial reduction in transistor count. It also shows improvements in delay when compared to two of the three published works

Designing a Novel High Performance Four-to-Two Compressor Cell Based on CNTFET Technology for Low Voltages

Compressor cell is often placed in critical path of multiplier circuits to perform partial product summation. Therefore it plays a significant role in determining the entire performance of multiplier and digital system. Respecting to the necessity of low power design for portable electronic, designing a low power and high performance compressors seems to be a good solution to overcome of these problems for computations. In this paper a novel high performance four-to-two compressor cell is proposed using Carbon Nanotube Field Effect Transistors (CNTFETs) technology. The new cell is based on Majority Function, NOR, and NAND gates. The main advantage of proposed design in comparison with former cells is the ease of obtaining CARRY output by means of Majority function. Simulations have been done with 32nm technology node using Synopsys HSPICE software. Simulation results confirm the priority of the proposed cell compared to other state-of-the-art four-to-two compressor cells

Design and Analysis of Multiplexer based Approximate Adder for Low Power Applications

Low power consumption is crucial for error-acceptable multimedia devices, with picture compression approaches leveraging various digital processing architectures and algorithms. Humans can assemble useful information from partially inaccurate outputs in many multimedia applications. As a result, producing exact outputs is not required. The demand for an exact outcome is fading because new innovative systems are forgiving of faults. In the domain where error-tolerance is accepted, approximate computing is a new paradigm that relaxes the requirement for an accurate modeling while offering power, time, and delay benefits. Adders are an essential arithmetic module for regulating power and memory usage in digital systems. The recent implementation and use of approximate adders have been supported by trade-off characteristics such as delay, lower power consumption. This study examines the delay and power consumption of conventional and approximate adders. Also, a simple, fast, and power-efficient multiplexer-based approximate adder is proposed, and its performance outperforms the adders compared with existing adders. The proposed adder can be utilized in error-tolerant and various digital signal processing applications where exact results are not required. The proposed and existing adders are designed using EDA software for the performance calculations. With a delay of 81 pS, the proposed adder circuit reduces power consumption compared to the exact one. The experiment shows that the designed approximate adder can be used to implement circuits for image processing systems because it has a smaller delay and uses less energy

Energy Efficient CNTFET Based Full Adder Using Hybrid Logic

Full Adder is the basic element for arithmetic operations used in Very Large Scale Integrated (VLSI) circuits, therefore, optimization of 1-bit full adder cell improves the overall performance of electronic devices. Due to unique mechanical and electrical characteristics, carbon nanotube field effect transistors (CNTFET) are found to be the most suitable alternative for metal oxide field effect transistor (MOSFET). CNTFET transistor utilizes carbon nanotube (CNT) in the channel region. In this paper, high speed, low power and reduced transistor count full adder cell using CNTFET 32nm technology is presented. Two input full swing XOR gate is designed using 4 transistors which is further used to generate Sum and Carry output signals with the help of Gate-Diffusion-Input (GDI) Technique thus reducing the number of transistors involved. Proposed design simulated in Cadence Virtuoso with 32nm CNTFET technology and results is better design as compared to existing circuits in terms of Power, Delay, Power-Delay-Product (PDP), Energy Consumption and Energy-Delay-Product (EDP)

High-Speed Area-Efficient Hardware Architecture for the Efficient Detection of Faults in a Bit-Parallel Multiplier Utilizing the Polynomial Basis of GF(2m)

The utilization of finite field multipliers is pervasive in contemporary digital systems, with hardware implementation for bit parallel operation often necessitating millions of logic gates. However, various digital design issues, whether natural or stemming from soft errors, can result in gate malfunction, ultimately leading to erroneous multiplier outputs. Thus, to prevent susceptibility to error, it is imperative to employ an effective finite field multiplier implementation that boasts a robust fault detection capability. This study proposes a novel fault detection scheme for a recent bit-parallel polynomial basis multiplier over GF(2m), intended to achieve optimal fault detection performance for finite field multipliers while simultaneously maintaining a low-complexity implementation, a favored attribute in resource-constrained applications like smart cards. The primary concept behind the proposed approach is centered on the implementation of a BCH decoder that utilizes re-encoding technique and FIBM algorithm in its first and second sub-modules, respectively. This approach serves to address hardware complexity concerns while also making use of Berlekamp-Rumsey-Solomon (BRS) algorithm and Chien search method in the third sub-module of the decoder to effectively locate errors with minimal delay. The results of our synthesis indicate that our proposed error detection and correction architecture for a 45-bit multiplier with 5-bit errors achieves a 37% and 49% reduction in critical path delay compared to existing designs. Furthermore, the hardware complexity associated with a 45-bit multiplicand that contains 5 errors is confined to a mere 80%, which is significantly lower than the most exceptional BCH-based fault recognition methodologies, including TMR, Hamming's single error correction, and LDPC-based procedures within the realm of finite field multiplication.Comment: 9 pages, 4 figures. arXiv admin note: substantial text overlap with arXiv:2209.1338

Techniques of Energy-Efficient VLSI Chip Design for High-Performance Computing

How to implement quality computing with the limited power budget is the key factor to move very large scale integration (VLSI) chip design forward. This work introduces various techniques of low power VLSI design used for state of art computing. From the viewpoint of power supply, conventional in-chip voltage regulators based on analog blocks bring the large overhead of both power and area to computational chips. Motivated by this, a digital based switchable pin method to dynamically regulate power at low circuit cost has been proposed to make computing to be executed with a stable voltage supply. For one of the widely used and time consuming arithmetic units, multiplier, its operation in logarithmic domain shows an advantageous performance compared to that in binary domain considering computation latency, power and area. However, the introduced conversion error reduces the reliability of the following computation (e.g. multiplication and division.). In this work, a fast calibration method suppressing the conversion error and its VLSI implementation are proposed. The proposed logarithmic converter can be supplied by dc power to achieve fast conversion and clocked power to reduce the power dissipated during conversion. Going out of traditional computation methods and widely used static logic, neuron-like cell is also studied in this work. Using multiple input floating gate (MIFG) metal-oxide semiconductor field-effect transistor (MOSFET) based logic, a 32-bit, 16-operation arithmetic logic unit (ALU) with zipped decoding and a feedback loop is designed. The proposed ALU can reduce the switching power and has a strong driven-in capability due to coupling capacitors compared to static logic based ALU. Besides, recent neural computations bring serious challenges to digital VLSI implementation due to overload matrix multiplications and non-linear functions. An analog VLSI design which is compatible to external digital environment is proposed for the network of long short-term memory (LSTM). The entire analog based network computes much faster and has higher energy efficiency than the digital one