Design and Noise Analysis of a Novel Auto-Zeroing Structure for Continuous-Time Instrumentation Amplifiers

This paper introduces a low-noise, low-power amplifier for high-impedance sensors. An innovative circuit using an auto-zeroed architecture combined with frequency modulation to reject offset and low-frequency noise is proposed and analysed. Special care was given to avoid broadband noise aliasing and chopping in the signal path, and to minimize both the resulting equivalent input offset voltage and equivalent input biasing current. The theoretical noise analysis of the proposed topology covers most of the noise sources of the circuit. Simulations show that the input-referred noise level of the circuit is 13.4nV/pHz for a power consumption of 85μA with a power supply from 1.8V to 3.6V

Low-Voltage and High-Fidelity Audio Sigma Delta ADC Utilizing a Resolution Enhanced Quantizer with Frequency Domain Technique

학위논문 (박사)-- 서울대학교 대학원 : 전기·컴퓨터공학부, 2014. 2. 김수환.This thesis proposes a way to design the multi-bit quantizer of sigma delta ADC with less number of comparators than that of the conventional design with performance improvement. The method uses error-feedback based sigma delta modulation and additional analog differentiator and a digital integrator. Applying this method to the quantizer of a sigma delta ADC, results in the quantizer resolution enhancement and the order of sigma delta modulator increment with high enough overall resolution enhancement enough to reduce the OSR of main sigma delta integrators. Based on the conventional design method, additional efforts added to precisely estimate the performance of designed sigma delta ADCs. The method is applied and confirmed in sigma delta ADC for consumer electrics audio application with less than 3 dB SNR difference. The ADC uses 3rd order, 256 OSR, 4 level quantizer to achieve over 90 dB SNR for audio applications. Psychoacoustic properties are concerned for better audible performance. Performance of SNR 94.3 dB and THD+N -91.3 dB are measured for the sigma delta ADC core. This ADC implemented on 0.13 μm CMOS mixed-signal process with 3.3 V supply voltage operation. The proposed quantizer is applied to a low voltage audio sigma delta ADC. The ADC uses 1.2 V supply voltage with 0.13 μm CMOS mixed-signal process. The 100 dB SNR ADC is designed using 2nd order, 64 OSR, the quantizer with 2 comparators and additional digital logics. As expected, the sigma delta modulator shows adequate signal to quantization noise ratio performance with the proposed quantizer so that OSR can be reduced. The design achieves 102.5 dB SNR and 99.4 dB SNDR.제１장 서론 제１절 연구의 목적 제２절 배경 이론 제１항 ADC 기초 제２항 오디오 신호의 특성과 ADC의 특성 제２장 고품질 디지털 오디오 시스템을 위한 시그마 델타 ADC 제１절 ADC 노이즈원의 배분 제１항 열 잡음 제２항 양자화 노이즈 제３항 1/f 노이즈 제２절 시그마 델타 변조기의 구조 제３절 회로 구현 제４절 설계 검증 제５절 측정 결과 제６절 결론 제３장 저 전압 동작에 적합한 양자화 장치를 기반으로 한 오디오 ADC 제１절 저 전압 소자 사용에 대한 고려 제２절 시그마 델타 변조기의 구조 제３절 검증을 위한 설계 목표 제４절 전체 구조 제５절 회로 구현 제６절 설계 검증 제７절 결론 제４장 결론 및 차후 계획 참고 자료 AbstractDocto

Doctor of Philosophy

dissertationTactile sensors are a group of sensors that are widely being developed for transduction of touch, force and pressure in the field of robotics, contact sensing and gait analysis. These sensors are employed to measure and register interactions between contact surfaces and the surrounding environment. Since these sensors have gained usage in the field of robotics and gait analysis, there is a need for these sensors to be ultra flexible, highly reliable and capable of measuring pressure and two-axial shear simultaneously. The sensors that are currently available are not capable of achieving all the aforementioned qualities. The goal of this work is to design and develop such a flexible tactile sensor array based on a capacitive sensing scheme and we call it the flexible tactile imager (FTI). The developed design can be easily multiplexed into a high-density array of 676 multi-fingered capacitors that are capable of measuring pressure and two-axial shear simultaneously while maintaining sensor flexibility and reliability. The sensitivity of normal and shear stress for the FTI are 0.74/MPa and 79.5/GPa, respectively, and the resolvable displacement and velocity are as low as 60 µm and 100 µm/s, respectively. The developed FTI demonstrates the ability to detect pressure and shear contours of objects rolling on top of it and capability to measure microdisplacement and microvelocities that are desirable during gait analysis

Realization of readout integrated circuit (ROIC) for an array of 72x4, P-on-N type HgCdTe long wave infrared detectors

Infrared Focal Plane Arrays (IRFPAs) are important and high-tech systems, which are used in many strategic applications, such as medical imaging, missile guidance, and surveillance systems. The most important building blocks of IRFPAs are detectors and Readout Integrated Circuit (ROIC). Both of them need careful design and implementation for the overall system to be succesful. Detector part produces the photon induced current and sent to the input of ROIC. Detector design and fabrication determines the operating wavelength and main noise performance of the imaging system. On the other hand, ROIC is the interface element between the detector and microcomputer of the IRFPA system, and determines important performance parameters of the overall system; such as linearity, dynamic range, injection efficiency, noise performance (less effective than detector), and power consumption. Therefore it is important to design and implement a ROIC, that fits best to the desired application. In this thesis, a CMOS ROIC is designed and implemented for scanning type of 72×4 Pon- N HgCdTe detector array in 0.35 μm, 4 metal 2 poly AMS CMOS process. Current Mirror Integration (CMI) is used as the unit cell of the ROIC. For the signal processing, Time Delay Integration (TDI) over 4 elements with an optical supersampling rate of 3 is used for improved Signal-to-Noise Ration (SNR). The designed and implemented ROIC has the properties of bidirectional scanning, variable integration time, adjustable gain settings, bypass functionality, automatic gain adjustment, and pixel selection/deselection functionality. ROIC is programmable through a serial and a parallel interface. Gain settings, TDI scanning direction, information of mulfunctioning pixels, ROIC operation mode (test or TDI) can be programmed by using these interfaces. Operating frequency of the ROIC is up to 5 MHz, while the dynamic range is 2.8 V

Realization of readout integrated circuit (ROIC) for an array of 288x4, N-on-P type HgCdTe long wave infrared detectors

Infrared (IR) imaging systems are used in a variety of applications from biomedical to astronomic and strategic imaging. Modern military missile guidance and surveillance systems also incorporate infrared imaging systems. The most critical component of an infrared imaging system is the focal plane array (FPA), a key assembly of detectors and readout electronics to carry out the function of infrared to electrical signal conversion. As in all sensor networks, extraordinary care must be given to both the detector design and readout integrated circuits, to obtain a high performance and durable system. In IRFPAs, detectors set the operation wavelength, readout circuit area and operation temperature. However many of the system performance parameters such as signal to noise ratio (SNR), linearity, input referred noise level, dynamic range, are set by the readout integrated circuit (ROIC). First generation of IR imaging systems incorporated single detector, or a fewer number of detectors. Higher frame rate and resolution requirements brought up the scanning type of FPAs where a scene is scanned constantly to create a 2D electronic image by a single array of detectors. Scanning type FPAs, with higher frame rates, started to replace staring arrays, with the maturing of detector processing technology and allowing integration of thousands of functioning detectors (pixels) on a single substrate, with smaller pitches. However, scanning type arrays are attractive due to their lower cost. In this thesis, design of a CMOS readout integrated circuit for an array of 288x4, n-on-p type HgCdTe long wave infrared detectors is presented. ROIC input preamplifier is current mirroring integration type due to low input impedance requirement. In order to increase SNR, time delay integration (TDI) on 4 detectors is applied with a super sampling rate of 3. ROIC has additional features of bidirectional TDI scanning, dead pixel deselection, automatic gain adjustment in response to pixel deselection, in addition to programmable four gain settings (up to 2.58pC storage), and programmable integration time. ROIC has four outputs with a dynamic range of 2.8V (from 1.7V to 4.5V) and input referred noise of 2989 electrons for an area of 13mm2. Two clocks: master clock and integration clock are required in order to operate the ROIC. Integration clock sets the integration time and adjust frame rate. Master clock maintains synchronization and can be adjusted up to 5MHz. ROIC can be programmed through both serial and parallel interface with full functionality but pixel deselection being allowed only in serial interface mode

Delta-sigma analog-to-digital converter for low-power microsensor applications

Piistä valmistetut pienoisanturit ovat yleistymässä niiden luotettavuuden, edullisuuden ja pienen koon ansiosta. Usein anturisysteemin lähtösignaalia halutaan käsitellä digitaalisena, mikä vaatii analogia-digitaalimuuntimen toteuttamisen. Systeemin integrointiasteen kasvattaminen on kannattavaa integroimalla rajapintaelektroniikka, mukaan lukien analogia-digitaalimuunnin, mahdollisimman lähelle anturielementtiä. Tämän työn tavoitteena on suunnitella ja toteuttaa analogia-digitaalimuunnin matalatehoiseen mikroanturisovellukseen. Työssä suunniteltiin kaksiasteinen deltasigma-analogia-digitaalimuunnin, joka käyttää kytkin-kondensaattoritekniikalla toteutettua silmukkasuodinta ja yksibittistä kvantisoijaa. Operaatiovahvistimen kohinan ja tulonsiirrosjännitteen vähentämiseksi muunnin käyttää erityistä korreloiva kaksoisnäytteistys -tekniikkaa ja tehon säästämiseksi tulon kaksoisnäytteistystä. Työssä esitellään myös onnistuneesti toteutettu korkeaimpedanssisen yhteismuodon jännitereferenssin käyttäminen tehon säästämiseksi. Piiri toteutettiin integroituna piirinä 0,35 µm:n CMOS-valmistusteknologialla. Työssä esitetään suunniteltu piiri ja sen mittaustulokset. Signaalikaistalla DC:ltä 1 kHz:iin piiri saavutti 83 dB:n signaali-kohinasuhteen ja 80 dB:n signaali-kohinasärösuhteen. Tuloon redusoiduksi kohinatiheydeksi mitattiin 1,3 µV/sqrt(Hz). Piiri kuluttaa 170 µW tehoa 3,6 V :n jännitelähteestä.Miniature sensors made of silicon are becoming common due to their reliability, low price and small size. Often the output signal of the sensor system is required in digital form, which necessitates the implementation of an analog-to-digital converter. Increasing the level of integration of the system by integrating the interface electronics, including the analog-to-digital converter, as close to the sensor element as possible, is beneficial. The goal of this work is to design and implement an analog-to-digital converter suitable for low power microsensor applications. A second order delta-sigma analog-to-digital converter using a switched capacitor loop filter with a single bit quantizer is designed. It utilizes a novel correlated double sampling technique for operational amplifier noise reduction and offset compensation, and input double sampling for power saving. Also, a high impedance common-mode voltage reference scheme for power saving is introduced and implemented successfully. The circuit was implemented as an integrated circuit in 0.35 µm CMOS process technology. The measurement results are reported and can be summarized as a 83 dB signal-to-noise ratio and a 80 dB signal-to-noise-and-distortion ratio, on a signal band from DC to 1 kHz. The input referred noise density of the noise floor is 1.3 µV/sqrt(Hz). The power consumption of the circuit is 170 µW from a 3.6 V voltage supply

Organic Photodiodes and Their Optoelectronic Applications

Recently, organic photodiodes (OPDs) have been acknowledged as a next-generation device for photovoltaic and image sensor applications due to their advantages of large area process, light weight, mechanical flexibility, and excellent photoresponse. This dissertation targets for the development and understanding of high performance organic photodiodes for their medical and industrial applications for the next-generation. As the first research focus, A dielectric / metal / dielectric (DMD) transparent electrode is proposed for the top-illumination OPDs. The fabricated DMD transparent electrode showed the maximum optical transmittance of 85.7 % with sheet resistance of 6.2 ohm/sq. In the second part of the thesis, a development of novel transfer process which enables the dark current suppression for the inverted OPD devices will be discussed. Through the effort, we demonstrated OPD with high D* of 4.82 x 10^12 Jones at reverse bias of 1.5 V with dark current density (Jdark) of 7.7 nA/cm2 and external quantum efficiency (EQE) of 60 %. Additionally in the third part, we investigate a high performance low-bandgap polymer OPD with broadband spectrum. By utilizing the novel transfer process to introduce charge blocking layers, significant suppression of the dark current is achieved while high EQE of the device is preserved. A low Jdark of 5 nA/cm2 at reverse bias of 0.5 V was achieved resulting in the highest D* of 1.5 x 10^13 Jones. To investigate the benefit for the various OPD applications, we developed a novel 3D printing technique to fabricate OPD on hemispherical concave substrate. The techniques allowed the direct patterning of the OPD devices on hemispherical substrates without excessive strain or deformation. Lastly, a simulation of the OPD stacked a-ITZO TFT active pixel sensor (APS) pixel with external transimpedance amplifier (TIA) readout circuit was performed.PHDElectrical & Computer Eng PhDUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/137168/1/hyunskim_1.pd

An energy efficient noise-shaping SAR ADC in 28 nm FDSOI

In a noise-shaping SAR ADC, oversampling and noise shaping are used to increase the conversion accuracy beyond that the SAR exhibits alone. To implement the noise shaping, the residue voltage present at the SAR DAC plates after each conversion is exploited, and fed into a loop filter connected to an extra input of the SAR comparator. In this thesis, an energy efficient noise-shaping SAR ADC for medical ultrasound applications is designed in 28 nm FDSOI. The design specification is minimum 11.0 bit ENOB of accuracy, signal bandwidth of minimum 2 MHz, and sample rate of minimum 32MHz. According to post-layout Monte Carlo simulations, the designed ADC has an accuracy of 11.1 bit ENOB, and thus satisfies the accuracy requirement. The signal bandwidth and sample rate are the same as in the design specification. Specifically, the topics of this thesis are the design of the loop filter and its inter- facing towards the SAR, as well as the overall high level design. The 9-bit SAR used in the system is an already existing implementation. A cascaded FIR-IIR filter topology is used for the loop filter. In this work, the circuit implementation of this topology is improved, most importantly through the introduction of chopped buffers at the filter input. This eliminates signal attenuation due to charge sharing, and a DAC capacitance that is smaller than the sampling capacitance in the loop filter can therefore be used. Also, auto-zeroed, cascoded inverters rather than a standard OTA are used as gain elements in the switched-capacitor filter structure, and this leads to better energy efficiency. The designed ADC achieves a figure of merit (FOM) of 7.5fJ/conv-step in post-layout Monte Carlo simulations, and to the best of the author s knowledge, this is better than the current state-of-the-art of noise-shaping ADCs. When all kinds of ADCs are taken into consideration, the achieved FOM seems to be similar to the current state-of-the-art in the same specification range

Disseny microelectrnic de circuits discriminadors de polsos pel detector LHCb

The aim of this thesis is to present a solution for implementing the front end system of the Scintillator Pad Detector (SPD) of the calorimeter system of the LHCb experiment that will start in 2008 at the Large Hadron Collider (LHC) at CERN. The requirements of this specific system are discussed and an integrated solution is presented, both at system and circuit level. We also report some methodological achievements. In first place, a method to study the PSRR (and any transfer function) in fully differential circuits taking into account the effect of parameter mismatch is proposed. Concerning noise analysis, a method to study time variant circuits in the frequency domain is presented and justified. This would open the possibility to study the effect of 1/f noise in time variants circuits. In addition, it will be shown that the architecture developed for this system is a general solution for front ends in high luminosity experiments that must be operated with no dead time and must be robust against ballistic deficit