Compensating mode conversion due to bend discontinuities through intentional trace asymmetry

In this letter, a comparative analysis is carried out between the mechanism of mode conversion in differential microstrip lines due to bend discontinuities on one side and trace asymmetry on the other side. With the help of equivalent modal circuits, a theoretical basis is provided for the idea to compensate the undesired common mode (CM), due to the presence of the bend, by intentionally designing asymmetric traces. As an application example, the proposed CM-reduction strategy is used in conjunction with another recently-presented wideband CM suppression filter for differential microstrip lines. It is shown that the proposed solution enhances the overall CM-reduction performance of the filter by some decibels, while preserving its transmission properties

Modeling and Analysis of Noise and Interconnects for On-Chip Communication Link Design

This thesis considers modeling and analysis of noise and interconnects in onchip communication. Besides transistor count and speed, the capabilities of a modern design are often limited by on-chip communication links. These links typically consist of multiple interconnects that run parallel to each other for long distances between functional or memory blocks. Due to the scaling of technology, the interconnects have considerable electrical parasitics that affect their performance, power dissipation and signal integrity. Furthermore, because of electromagnetic coupling, the interconnects in the link need to be considered as an interacting group instead of as isolated signal paths. There is a need for accurate and computationally effective models in the early stages of the chip design process to assess or optimize issues affecting these interconnects. For this purpose, a set of analytical models is developed for on-chip data links in this thesis. First, a model is proposed for modeling crosstalk and intersymbol interference. The model takes into account the effects of inductance, initial states and bit sequences. Intersymbol interference is shown to affect crosstalk voltage and propagation delay depending on bus throughput and the amount of inductance. Next, a model is proposed for the switching current of a coupled bus. The model is combined with an existing model to evaluate power supply noise. The model is then applied to reduce both functional crosstalk and power supply noise caused by a bus as a trade-off with time. The proposed reduction method is shown to be effective in reducing long-range crosstalk noise. The effects of process variation on encoded signaling are then modeled. In encoded signaling, the input signals to a bus are encoded using additional signaling circuitry. The proposed model includes variation in both the signaling circuitry and in the wires to calculate the total delay variation of a bus. The model is applied to study level-encoded dual-rail and 1-of-4 signaling. In addition to regular voltage-mode and encoded voltage-mode signaling, current-mode signaling is a promising technique for global communication. A model for energy dissipation in RLC current-mode signaling is proposed in the thesis. The energy is derived separately for the driver, wire and receiver termination.Siirretty Doriast

Low-Power, High-Speed Transceivers for Network-on-Chip Communication

Networks on chips (NoCs) are becoming popular as they provide a solution for the interconnection problems on large integrated circuits (ICs). But even in a NoC, link-power can become unacceptably high and data rates are limited when conventional data transceivers are used. In this paper, we present a low-power, high-speed source-synchronous link transceiver which enables a factor 3.3 reduction in link power together with an 80% increase in data-rate. A low-swing capacitive pre-emphasis transmitter in combination with a double-tail sense-amplifier enable speeds in excess of 9 Gb/s over a 2 mm twisted differential interconnect, while consuming only 130 fJ/transition without the need for an additional supply. Multiple transceivers can be connected back-to-back to create a source-synchronous transceiver-chain with a wave-pipelined clock, operating with 6sigma offset reliability at 5 Gb/s

System for Suppressing Vibration in Turbomachine Components

Disclosed is a system for suppressing vibration and noise mitigation in structures such as blades in turbomachinery. The system includes flexible piezoelectric patches which are secured on or imbedded in turbomachinery blades which, in one embodiment, comprises eight (8) fan blades. The system further includes a capacitor plate coupler and a power transfer apparatus, which may both be arranged into one assembly, that respectively transfer data and power. Each of the capacitive plate coupler and power transfer apparatus is configured so that one part is attached to a fixed member while another part is attached to a rotatable member with an air gap there between. The system still further includes a processor that has 16 channels, eight of which serve as sensor channels, and the remaining eight, serving as actuation channels. The processor collects and analyzes the sensor signals and, in turn, outputs corrective signals for vibration/noise suppression of the turbine blades

Signal Integrity Analysis for High Speed Digital Circuit

This dissertation report marks the commencement of the Final Year Project (FYP) titled Signal Integrity Analysis for High Speed Digital Circuit. This project is a study on various signal integrity (SI) issues that could possibly come into play on Printed Circuit Boards (PCBs). This project is conducted to analyze and grasp a better understanding on the nature of the problem, how the problem is manifested in circuits and what design solutions can be employed to minimize its effects. Such a study is not something new but is definitely getting more crucial as the vast improvement in chip fabrication technology leads to logic families operating at a much higher speed, resulting to a faster rise time which will worsen the noise phenomena, i. e. reflection, crosstalk, and power system stability during component switching. Several causes to signal integrity issues on the printed circuit boards are analyzed and both proper and improper circuit design techniques are implemented on the Advanced Design System (ADS) software for data collection and analysis. Deliverables at the end this project would be the simulation results to support the study, whereby several simulations are conducted to demonstrate and verify the theoretical study of signal integrity issues. Besides that, the designs will then be fabricated on a two-layer microstrip board and tested on the Digital Communication Analyzer (DCA) to obtain more practical results. A project Gantt chart is attached in the appendix to illustrate the work flow and anticipated progress

Analysis of Switching Voltage Regulator Noise Coupling to a High-Speed Signal

In this paper, a real-world signal and power integrity problem due to the switching noise of buck converter IC coupling to a high-speed signal line in a server system is studied. The rapid switching field effect transistors (FETs) of the voltage regulator module (VRM) are the main source of the performance degradation on the nearby signal lines. A simplified mock-up simulation setup is proposed based on the actual board design to investigate the coupling mechanism of the VRM noise. The mechanism of the switching noise coupling is explained with the phenomenon of capacitive and inductive coupling. Based on this finding, the solutions will be identified as decreasing the inductive coupling by optimizing the board layout