NoC Synthesis Flow for Customized Domain Specific Mutliprocessor Systems-on-Chip

The growing complexity of customizable single-chip multiprocessors is requiring communication resources that can only be provided by a highly-scalable communication infrastructure. This trend is exemplified by the growing number of network-on-chip (NoC) architectures that have been proposed recently for system-on-chip (SoC) integration. Developing NoC-based systems tailored to a particular application domain is crucial for achieving high-performance, energy-efficient customized solutions. The effectiveness of this approach largely depends on the availability of an ad hoc design methodology that, starting from a high-level application specification, derives an optimized NoC configuration with respect to different design objectives and instantiates the selected application specific on-chip micronetwork. Automatic execution of these design steps is highly desirable to increase SoC design productivity. This work illustrates a complete synthesis flow, called Netchip, for customized NoC architectures, that partitions the development work into major steps (topology mapping, selection, and generation) and provides proper tools for their automatic execution (SUNMAP, xpipescompiler). The entire flow leverages the flexibility of a fully reusable and scalable network components library called xpipes, consisting of highly-parameterizable network building blocks (network interface, switches, switch-to-switch links) that are design-time tunable and composable to achieve arbitrary topologies and customized domain-specific NoC architectures. Several experimental case studies are presented In the work, showing the powerful design space exploration capabilities of the proposed methodology and tools

Proposition of a benchmark for evaluation of cores mapping onto NoC architectures

Proposition of a MC-CDMA Radiocommunication benchmark for evaluation of cores mapping onto NoC architectures. Illustration with CEA-LETI FAUST NoC in the context of 4-more European project

Програмна модель мереж на кристалі із нерегулярними топологіями

The review of different approaches to the simulation of the networks-on-chip (NoC) is performed. The simulator of the NoC where the topology is set with the matrix of connections between the routers that manage the traffic by means of the routing tables is developed. The capabilities of the NoC simulator are examined and the results of its approbation by the example of the regular and quasi-optimal NoCs are presentedПроведен обзор различных подходов к моделированию сетей на кристалле (СтнК). Разработан симулятор СтнК, где топология задается матрицей связей между роутерами, которые управляют трафиком с помощью таблиц маршрутизации. Рассмотрены возможности симулятора СтнК и представлены результаты его апробации на примере регулярных и квазиоптимальных сетейПроведено огляд різних підходів до моделювання мереж на кристалі (МнК). Розроблено симулятор МнК, у якому топологія задається матрицею зв’язків між роутерами, що керують трафіком за допомогою таблиць маршрутизації. Розглянуто можливості симулятора МнК та представлені результати його апробації на прикладі регулярних і квазіоптимальних мере

A Topology Design Customization Approach for STNoC

To support high bandwidth SoCs, a communication design flow is necessary for the design space exploration respecting tight design requirements. In order to exploit the benefits introduced by the NoC approach for the on-chip communication, the paper presents a design flow for the core mapping and customization of the network topology applied to STNoC, the Network on-Chip developed by STMicroelectronics. Starting from ring topology, the proposed application-specific flow tries to find a set of customized topologies, optimized in terms of performance and area/energy overhead, by adding links. The generated STNoC custom topologies provide a reduced cost with respect to the spidergon topology