A review of advances in pixel detectors for experiments with high rate and radiation

The Large Hadron Collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the High Luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. This paper reviews the world-wide effort on these developments.Comment: 84 pages with 46 figures. Review article.For submission to Rep. Prog. Phy

Modeling of reverse current effects in trench-based smart power technologies

The increase in complexity in todays automotive products is driven by the trend to implement new features in the area of safety, comfort and entertainment. This significantly raises the safety requirements of new ICs and the identification of possible sources of failures gains in priority. One of these failure sources is the injection of parasitic currents into the common substrate of a chip. This does not only occur during exceptions in the operation of the IC but also affects applications which require switching of inductive loads. The difficulty to handle substrate current injection originates from its nonlocality as it potentially influences the entire IC. In this thesis a point-to-point modeling scheme for Spice-based circuit simulation is proposed. It addresses parasitic coupling effects caused by minority carrier injection into the substrate of a deep-trench based BCD technology. Since minority carriers can diffuse over large distances in the common substrate and disturb circuits in their normal operation, a quantitative approach is necessary to address this parasitic effect early during design. An equivalent circuit based on the chip's design is extracted and the coupling effect between the perturbing devices and the susceptible nodes is represented by Verilog-AMS models. These models represent the three main components in the coupling path which are the forward biased diode at the perturbing device, the reverse biased diode at the susceptible node, and the intermediary common substrate of the chip. An automated layout extraction framework identifies the injectors of the minority carriers and the sensitive devices. Additionally, it determines the relevant parameters for the models. The curve fitting functions of the models are derived from calibrated TCAD simulations which are based on the measurement results of two dedicated test chips. The test chips were specifically designed to provide detailed analysis capabilities of this parasitic coupling effect. This led to a design which contains several different injector nodes and a large number of susceptible nodes spread over the entire area of the chip. Additionally, the chip incorporates the most commonly used layout-based guard structures to obtain an in-depth insight on their efficiency in recent BCD technologies. Based on the results obtained by measurements of the test chips the underlying physics of the coupling effect are discussed in detail. Minority carrier injection in the substrate is not much different to the operating principle of a bipolar transistor and the differences and similarities between them are presented. This forms the basis of the model development and explains how the equations of the Verilog-AMS models were derived. Finally, the entire simulation flow is evaluated and the simulation results are compared to measurements of the chip

Integralni pristup sustavima energetske elektronike

Today\u27s power electronics systems are typically manufactured using non-standard parts, resulting in labor-intensive manufacturing processes, increased cost and poor reliability. As a possible way to overcome these problems, this paper discusses an integrated approach to design and manufacture power electronics systems to improve performance, reliability and cost effectiveness. Addressed in the paper are the technologies being developed for integration of both power supplies and motor drives. These technologies include the planar metalization to eliminate bonding wires, the integration of power passives, the integration of current sensors, the development of power devices to facilitate integration as well as to improve performance, and the integration of necessary CAD tools to address the multidisciplinary aspects of integrated systems. The development of Integrated Power Electronics Modules (IPEMs) is demonstrated for two applications: (1) 1 kW asymmetrical half-bridge DC-DC converter and (2) 1–3 kW motor drive for heating, ventilation and air conditioning (HVAC). Electrical and thermal design tradeoffs of IPEMs and related enabling technologies are described in the paper.Današnji sustavi energetske elektronike se obično proizvode iz nestandardnih dijelova. Posljedica toga je laboratorijska proizvodnja elektroničkih učinskih pretvarača, povećani troškovi i smanjena pouzdanost. Jedan od mogućih načina prevladavanja ovih poteškoća jest integralni pristup projektiranju i proizvodnji sustava energetske elektronike. Posebice se razmatraju tehnologije razvijene za integraciju učinskih krugova i motora. Ove tehnologije uključuju postupke planarne metalizacije za izbjegavanje žičanih vodova, integraciju pasivnih dijelova učinskih krugova, integraciju strujnih senzora, te razvoj takvih poluvodičkih komponenata koje olakšavaju integraciju i poboljšavaju karakteristike uređaja. Pri projektiranju, zbog multidisciplinarnih aspekata integriranih sustava, treba primijeniti nužne CAD alate. Razvoj integriranih modula elektroničkih učinskih pretvarača (engl. integrated power electronics modules, IPEM) ilustriran je na dvije primjene: (1) istosmjerni pretvarač snage 1 kW u asimetričnom polumosnom spoju i (2) elektromotorni pogon snage 1 . . . 3 kW za grijanje, ventilaciju i klimatizaciju (engl. heating, ventilation and air conditioning, HVAC). Na IPEM-u objašnjeni su projektantski i tehnološki kompromisi električkog i toplinskog projekta

Lateral Power Mosfets Hardened Against Single Event Radiation Effects

The underlying physical mechanisms of destructive single event effects (SEE) from heavy ion radiation have been widely studied in traditional vertical double-diffused power MOSFETs (VDMOS). Recently lateral double-diffused power MOSFETs (LDMOS), which inherently provide lower gate charge than VDMOS, have become an attractive option for MHz-frequency DC-DC converters in terrestrial power electronics applications [1]. There are growing interests in extending the LDMOS concept into radiation-hard space applications. Since the LDMOS has a device structure considerably different from VDMOS, the well studied single event burn-out (SEB) or single event gate rapture (SEGR) response of VDMOS cannot be simply assumed for LDMOS devices without further investigation. A few recent studies have begun to investigate ionizing radiation effects in LDMOS devices, however, these studies were mainly focused on displacement damage and total ionizing dose (TID) effects, with very limited data reported on the heavy ion SEE response of these devices [2]-[5]. Furthermore, the breakdown voltage of the LDMOS devices in these studies was limited to less than 80 volts (mostly in the range of 20-30 volts), considerably below the voltage requirement for some space power applications. In this work, we numerically and experimentally investigate the physical insights of SEE in two different fabricated LDMOS devices designed by the author and intended for use in radiation hard applications. The first device is a 24 V Resurf LDMOS fabricated on P-type epitaxial silicon on a P+ silicon substrate. The second device is a iv much different 150 V SOI Resurf LDMOS fabricated on a 1.0 micron thick N-type silicon-on-insulator substrate with a 1.0 micron thick buried silicon dioxide layer on an N-type silicon handle wafer. Each device contains internal features, layout techniques, and process methods designed to improve single event and total ionizing dose radiation hardness. Technology computer aided design (TCAD) software was used to develop the transistor design and fabrication process of each device and also to simulate the device response to heavy ion radiation. Using these simulations in conjunction with experimentally gathered heavy ion radiation test data, we explain and illustrate the fundamental physical mechanisms by which destructive single event effects occur in these LDMOS devices. We also explore the design tradeoffs for making an LDMOS device resistant to destructive single event effects, both in terms of electrical performance and impact on other radiation hardness metric

High-voltage SiC power devices for improved energy efficiency

Silicon carbide (SiC) power devices significantly outperform the well-established silicon (Si) devices in terms of high breakdown voltage, low power loss, and fast switching. This review briefly introduces the major features of SiC power devices and then presents research works on breakdown phenomena in SiC pn junctions and related discussion which takes into account the energy band structure. Next, recent progress in SiC metal-oxide-semiconductor field effect transistors, which are the most important unipolar devices, is described with an emphasis on the improvement of channel mobility at the SiO2/SiC interface. The development of SiC bipolar devices such as pin diodes and insulated gate bipolar transistors, which are promising for ultrahigh-voltage (>10 kV) applications, are introduced and the effect of carrier lifetime enhancement is demonstrated. The current status of mass production and how SiC power devices can contribute to energy saving are also described

Prikaz stanja silicijevih MOS upravljanih učinskih sklopova i PiN ispravljača

Revolutionary advances and developments have been made in power semiconductor device technologies during the last decades which have allowed the improvement of power electronic systems in terms of their efficiency and reliability. The advent of MOS-gated power switches such as the power MOSFET and the IGBT showing high input impedance has been a real breakthrough in the design and fabrication of power electronic systems. This paper reviews the recent progress in the development of Si MOS-gated power devices and rectifiers. The evolution of these devices’ technologies together with the introduction of revolutionary device concepts is also discussed. Concretely, the introduction of trench technologies for power MOSFETs and the use of the super-junction concept for breaking the 1D-silicon limit are highlighted. Developments in IGBTs such as those based on the use of thin wafers and strategies for optimising the plasma distribution in PT IGBTs during the on-state are also addressed. Finally, advances in PiN diode technologies including new concepts for both the anode and the cathode structures are also reviewed. These approaches have allowed the reduction of the PiN total losses and a soft reverse recovery behaviour, leading to a more rugged device.U posljednjim desetljećima svjedočimo razvoju sustava učinske elektronike u pogledu povećanja efikasnosti i pouzdanosti. Napredak je omogućen zahvaljujući izvanrednom napredku koji je postignut na području učinskih poluvodiča. Pojava MOS upravljanih učinskih sklopova s visokom ulaznom impedancijom, kao što su MOSFET i IGBT, rezultirao je probojem u projektiranju i proizvodnji sustava učinske elekronike. Ovaj članak daje uvid u napredak koji je u posljednje vrijeme ostvaren u razvoju silicijeve MOS upravljane učinske elektronike i ispravljača. Uz dosadašnji razvoj tehnologije navedenih komponenata, u članku je uključen i osvrt na revolucionarne koncepte budućeg razvoja. Konkretno, u radu su objašnjene tehnologija rova za MOSFET i korištenje koncepta super spoja za probijanje granice jednodimenzionalnog silicija. Razmatrana su i poboljšanja IGBT-ova koja se baziraju na uporabi tankih pločica a strategijama optimiranja distribucije plazme u PT IGBT-ovima za vrijeme aktivnog stanja. Konačno, prikazan je i napredak u tehnologiji PiN dioda koji uključuje nove strukturalne koncepte katode i anode. Ovi pristupi su omogućili smanjenje ukupnih gubitaka PiN diode i blagu dinamiku reverznog oporavka, što rezultira povećanjem robusnosti sklopa

Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications

Im Rahmen der vorliegenden Dissertation zum Thema „Through-Silicon Vias in SiGe BiCMOS and Interposer Technologies for Sub-THz Applications“ wurde auf Basis einer 130 nm SiGe BiCMOS Technologie ein Through-Silicon Via (TSV) Technologiemodul zur Herstellung elektrischer Durchkontaktierungen für die Anwendung im Millimeterwellen und Sub-THz Frequenzbereich entwickelt. TSVs wurden mittels elektromagnetischer Simulationen modelliert und in Bezug auf ihre elektrischen Eigenschaften bis in den sub-THz Bereich bis zu 300 GHz optimiert. Es wurden die Wechselwirkungen zwischen Modellierung, Fertigungstechnologie und den elektrischen Eigenschaften untersucht. Besonderes Augenmerk wurde auf die technologischen Einflussfaktoren gelegt. Daraus schlussfolgernd wurde das TSV Technologiemodul entwickelt und in eine SiGe BiCMOS Technologie integriert. Hierzu wurde eine Via-Middle Integration gewählt, welche eine Freilegung der TSVs von der Wafer Rückseite erfordert. Durch die geringe Waferdicke von ca. 75 μm wird einen Carrier Wafer Handling Prozess verwendet. Dieser Prozess wurde unter der Randbedingung entwickelt, dass eine nachfolgende Bearbeitung der Wafer innerhalb der BiCMOS Pilotlinie erfolgen kann. Die Rückseitenbearbeitung zielt darauf ab, einen Redistribution Layer auf der Rückseite der BiCMOS Wafer zu realisieren. Hierzu wurde ein Prozess entwickelt, um gleichzeitig verschiedene TSV Strukturen mit variablen Geometrien zu realisieren und damit eine hohe TSV Design Flexibilität zu gewährleisten. Die TSV Strukturen wurden von DC bis über 300 GHz charakterisiert und die elektrischen Eigenschaften extrahiert. Dabei wurde gezeigt, dass TSV Verbindungen mit sehr geringer Dämpfung <1 dB bis 300 GHz realisierbar sind und somit ausgezeichnete Hochfrequenzeigenschaften aufweisen. Zuletzt wurden vielfältige Anwendungen wie das Grounding von Hochfrequenzschaltkreisen, Interposer mit Waveguides und 300 GHz Antennen dargestellt. Das Potential für Millimeterwellen Packaging und 3D Integration wurde evaluiert. TSV Technologien sind heutzutage in vielen Anwendungen z.B. im Bereich der Systemintegration von Digitalschaltkreisen und der Spannungsversorgung von integrierten Schaltkreisen etabliert. Im Rahmen dieser Arbeit wurde der Einsatz von TSVs für Millimeterwellen und dem sub-THz Frequenzbereich untersucht und die Anwendung für den sub-THz Bereich bis 300 GHz demonstriert. Dadurch werden neue Möglichkeiten der Systemintegration und des Packaging von Höchstfrequenzsystemen geschaffen.:Bibliographische Beschreibung List of symbols and abbreviations Acknowledgement 1. Introduction 2. FEM Modeling of BiCMOS & Interposer Through-Silicon Vias 3. Fabrication of BiCMOS & Silicon Interposer with TSVs 4. Characterization of BiCMOS Embedded Through-Silicon Vias 5. Applications 6. Conclusion and Future Work 7. Appendix 8. Publications & Patents 9. Bibliography 10. List of Figures and Table

Advances on CMOS image sensors

This paper offers an introduction to the technological advances of image sensors designed using complementary metal–oxide–semiconductor (CMOS) processes along the last decades. We review some of those technological advances and examine potential disruptive growth directions for CMOS image sensors and proposed ways to achieve them. Those advances include breakthroughs on image quality such as resolution, capture speed, light sensitivity and color detection and advances on the computational imaging. The current trend is to push the innovation efforts even further as the market requires higher resolution, higher speed, lower power consumption and, mainly, lower cost sensors. Although CMOS image sensors are currently used in several different applications from consumer to defense to medical diagnosis, product differentiation is becoming both a requirement and a difficult goal for any image sensor manufacturer. The unique properties of CMOS process allows the integration of several signal processing techniques and are driving the impressive advancement of the computational imaging. With this paper, we offer a very comprehensive review of methods, techniques, designs and fabrication of CMOS image sensors that have impacted or might will impact the images sensor applications and markets

High performance 3-folded symmetric decoupled MEMS gyroscopes

This thesis reports, for the first time, on a novel design and architecture for realizing inertial grade gyroscope based on Micro-Electro-Mechanical Systems (MEMS) technology. The proposed device is suitable for high-precision Inertial Navigation Systems (INS). The new design has been investigated analytically and numerically by means of Finite Element Modeling (FEM) of the shapes, resonance frequencies and decoupling of the natural drive and sense modes of the various implementations. Also, famous phenomena known as spring softening and spring hardening are studied. Their effect on the gyroscope operation is modeled numerically in Matlab/Simulink platform. This latter model is used to predict the drive/sense mode matching capability of the proposed designs. Based on the comparison with the best recently reported performance towards inertial grade operation, it is expected that the novel architecture further lowers the dominant Brownian (thermo-mechanical) noise level by more than an order of magnitude (down to 0.08º/hr). Moreover, the gyroscope\u27s figure of merit, such as output sensitivity (150 mV/º/s), is expected to be improved by more than two orders of magnitude. This necessarily results in a signal to noise ratio (SNR) which is up to three orders of magnitude higher (up to 1,900mV/ º/hr). Furthermore, the novel concept introduced in this work for building MEMS gyroscopes allows reducing the sense parasitic capacitance by up to an order of magnitude. This in turn reduces the drive mode coupling or quadrature errors in the sensor\u27s output signal. The new approach employs Silicon-on-Insulator (SOI) substrates that allows the realization of large mass (\u3e1.6mg), large sense capacitance (\u3e2.2pF), high quality factors (\u3e21,000), large drive amplitude (~2-4 µm) and low resonance frequency (~3-4 KHz) as well as the consequently suppressed noise floor and reduced support losses for high-performance vacuum operation. Several challenges were encountered during fabrication that required developing high aspect ratio (up to 1:20) etching process for deep trenches (up to 500 µm). Frequency Response measurement platform was built for devices characterization. The measurements were performed at atmospheric pressures causing huge drop of the devices performance. Therefore, various MEMS gyroscope packaging technologies are studied. Wafer Level Packaging (WLP) is selected to encapsulate the fabricated devices under vacuum by utilizing wafer bonding. Through Silicon Via (TSV) technology was developed (as connections) to transfer the electrical signals (of the fabricated devices) outside the cap wafers

Design Techniques of Highly Integrated Hybrid-Switched-Capacitor-Resonant Power Converters for LED Lighting Applications

The Light-emitting diodes (LEDs) are rapidly emerging as the dominant light source given their high luminous efficacy, long lift span, and thanks to the newly enacted efficiency standards in favor of the more environmentally-friendly LED technology. The LED lighting market is expected to reach USD 105.66 billion by 2025. As such, the lighting industry requires LED drivers, which essentially are power converters, with high efficiency, wide input/output range, low cost, small form factor, and great performance in power factor, and luminance flicker. These requirements raise new challenges beyond the traditional power converter topologies. On the other hand, the development and improvement of new device technologies such as printed thin-film capacitors and integrated high voltage/power devices opens up many new opportunities for mitigating such challenges using innovative circuit design techniques and solutions. Almost all electric products needs certain power delivery, regulation or conversion circuits to meet the optimized operation conditions. Designing a high performance power converter is a real challenge given the market’s increasing requirements on energy efficiency, size, cost, form factor, EMI performance, human health impact, and so on. The design of a LED driver system covers from high voltage AC/DC and DC/DC power converters, to high frequency low voltage digital controllers, to power factor correction (PFC) and EMI filtering techniques, and to safety solutions such as galvanic isolation. In this thesis, we study design challenges and present corresponding solutions to realize highly integrated and high performance LED drivers combining switched-capacitor and resonant converters, applying re-configurable multi-level circuit topology, utilizing sigma delta modulation, and exploring capacitive galvanic isolation. A hybrid switched-capacitor-resonant (HSCR) LED driver based on a stackable switched-capacitor (SC) converter IC rated for 15 to 20 W applications. Bulky transformers have been replaced with a SC ladder to perform high-efficiency voltage step-down conversion; an L-C resonant output network provides almost lossless current regulation and demonstrates the potential of capacitive galvanic isolation. The integrated SC modules can be stacked in the voltage domain to handle a large range of input voltage ranges that largely exceed the voltage limitation of the medium-voltage-rated 120 V silicon technology. The LED driver demonstrates > 91% efficiency over a rectified input DC voltage range from 160 VDC to 180 VDC with two stacked ICs; using a stack of four ICs > 89.6% efficiency is demonstrated over an input range from 320 VDC to 360 VDC . The LED driver can dim its output power to around 10% of the rated power while maintaining >70% efficiency with a PWM controlled clock gating circuit. Next, the design of AC main rectifier and inverter front end with sigma delta modulation is described. The proposed circuits features a pair of sigma delta controlled multilevel converters. The first is a multilevel rectifier responsible for PFC and dimming. The second is a bidirectional multilevel inverter used to cancel AC power ripple from the DC bus. The system also contains an output stage that powers the LEDs with DC and provides for galvanic isolation. Its functional performance indicates that integrated multilevel converters are a viable topology for lighting and other similar applications